DS1558
Watchdog Clock with NV RAM Control
www.maxim-ic.com
FEATURES
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Integrated real-time clock (RTC), power-fail
control circuit, and NV RAM controller
Clock registers are accessed identically to the
static RAM; these registers are resident in the
16 top RAM locations
Century register
Greater than 10 years of timekeeping and data
retention in the absence of power with small
lithium coin cell(s) and low-leakage SRAM
Precision power-on reset
Programmable watchdog timer and RTC
alarm
BCD-coded year, month, date, day, hours,
minutes, and seconds with automatic leap-
year compensation valid up to the year 2100
Battery voltage-level indicator flag
Power-fail write protection allows for
鹵10%
V
CC
power-supply tolerance
Underwriters Laboratory (UL) recognized
PIN CONFIGURATION
TOP VIEW
GND
X1
X2
GND
A17
N.C.
VCC
N.C.
VCCO
NC
RST
VBAT
2
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Package Dimension Information:
www.maxim-ic.com/DallasPackInfo
PIN DESCRIPTION
A0鈥揂18
DQ0鈥揇Q7
IRQ
/FT
RST
CE
CER
OE
OER
WE
ORDERING INFORMATION
PART
DS1558Y
DS1558W
PIN-
PACKAGE
48 TQFP
48 TQFP
V
CC
(V)
5
3.3
TOP
MARK
DS1558B
DS1558D
V
CC
V
CCO
GND
N.C.
X1, X2
V
BAT1
V
BAT2
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata..
1 of 18
N.C.
A0
DQ0
DQ1
DQ2
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CER
13
14
15
16
17
18
19
20
21
22
23
24
N.C.
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
DS1558
A15
VBAT1
WE
IRQ/FT
A13
A8
A9
A11
OE
A10
CE
OER
TQFP
- Address Input
- Data Input/Outputs
- Interrupt, Frequency-Test
Output (Open Drain)
- Power-On Reset Output
(Open Drain)
- Chip-Enable Input
- Chip-Enable RAM
- Output-Enable Input
- Output-Enable RAM
- Write Enable
- Power-Supply Input
- V
CC
Out to RAM
- Ground
- No Connection
- Crystal Connection
- +3V Battery Input
- +3V Battery Input
REV: 082503