4 Megabit CMOS SRAM
DPS512S8U
DESCRIPTION:
The DPS512S8U is a 512K X 8 high-density, low-power static RAM
module comprised of four 128K X 8 monolithic SRAM鈥檚, an
advanced high-speed CMOS decoder and decoupling capacitors
surface mounted on an epoxy laminate substrate.
The DPS512S8U operates from a single +5V supply and all input
and output pins are completely TTL-compatible. The low standby
power of the DPS512S8U makes it ideal for battery-backed
applications.
FEATURES:
鈥?/div>
524, 288 by 8 Bit Configuration
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Access Times:
70, 85, 100, 120, 150ns
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Low Power Dissipation:
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40
碌
W (typ.) Standby
375 mW (typ.) Operating
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2-Volt Data Retention
鈥?/div>
Fully Static Operation
- No Clock or Refresh Required
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All inputs and Outputs are TTL-Compatible
鈥?/div>
36-PIN Plastic SIP Package
PIN NAMES
A0 - A18
I/O0 - I/O7
CE
WE
OE
V
DD
V
SS
N.C.
Address Inputs
Data In/Out
Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
No Connect
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
30A082-00
REV. D
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
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