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DP84910VHG-36 Datasheet

  • DP84910VHG-36

  • Integrated Read Channel

  • 32頁

  • NSC

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DP84910 (-36 -50) Integrated Read Channel
October 1994
DP84910 (-36 -50)
Integrated Read Channel
General Description
The DP84910 integrates most functions of the hard disk
read channel electronics onto a single 5V chip It incorpo-
rates a pulse servo detector a programmable integrated
channel filter a data synchronizer a frequency synthesizer
and a serial port interface The chip receives data from a
read preamplifier filters and peak detects the read pulses
for both data and embedded servo information and resyn-
chronizes the data with the system clock
The DP84910 is available in two versions DP84910VHG-36
and DP84910VHG-50 The DP84910VHG-36 is specified to
operate over a data rate range of 7 5 Mbits sec to
36 Mbits sec The other version DP84910VHG-50 will op-
erate over a data rate range of 13 7 Mbits sec to 50 Mbits
sec
This device is specifically designed to address zoned data
rate applications A channel filter with control register se-
lectable cutoff frequency and equalization is provided on-
chip This eliminates the need for multiple external channel
filters and allows for greater flexibility in the selection of
zone frequencies The frequency synthesizer provides cen-
ter frequency information for the data synchronizer and a
variable frequency write clock There is no need for any off-
chip frequency setting components or DACs
A four-bank control register is included to control zoning
operations and configure general chip functions At V
CC
power-up the chip self-configures by presetting all bits in the
control register to predetermined operating setup condi-
tions
Independent power down control for all of the major blocks
within the chip is provided via three bits in the control
register
(SYNC PWR DN
STH PWR DN
and
PD PWR DN) to manage power consumption In addi-
tion two pins (SLEEP and IDLE SERVO) are available to
control power management The sleep mode pin (SLEEP)
powers down all circuitry on the chip including the control
register In this mode the maximum power supply current is
2 mA the control register data must be reentered when
exiting this mode The idle servo mode pin (IDLE SERVO)
toggles the device between the idle and servo modes In the
idle mode only the control register and pulse detector bias-
ing circuitry necessary for a quick recovery are active In the
servo mode the pulse detector portions needed for servo
detection are active as well as the control register Less
than 15
ms
is required for the pulse detector to recover from
the idle condition The control register data is not lost when
this pin is toggled The pin can be rapidly toggled (
k
15
ms)
to achieve average power consumption savings and will
keep the read write head on track Seventeen power and
ground pins are provided to isolate major functional blocks
and allow for independent supply voltage filtering thus en-
hancing noise immunity
(Continued)
TL F 11777 鈥?1
FIGURE 1 DP84910 in a Typical Disk Drive System
MICROWIRE
TM
is a trademark of National Semiconductor Corporation
C
1996 National Semiconductor Corporation
TL F 11777
RRD-B30M116 Printed in U S A
http
www national com

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