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DP8480A Datasheet

  • DP8480A

  • DP8480A 10k ECL to TTL Level Translator with Latch

  • 6頁

  • NSC

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DP8480A 10k ECL to TTL Level Translator with Latch
April 1990
DP8480A 10k ECL to TTL Level Translator with Latch
General Description
This circuit translates ECL input levels to TTL output levels
and provides a fall-through latch The TRI-STATE outputs
are designed to drive standard 50 pF loads The strobe and
chip select inputs operate at ECL levels
Features
Y
Y
Y
Y
Y
Y
16-pin DIP
TRI-STATE outputs
ECL control inputs
8 ns typical propagation delay with 50 pF load
Outputs are TRI-STATE during power up down for
glitch free operation
10k ECL input compatible
Logic and Connection Diagram
Dual-In-Line Package
Truth Table
D
H
L
X
X
Q
L
H
Q
Hi-Z
STR
L
L
H
X
CS
L
L
L
H
H
e
high level (most positive)
L
e
low level (most negative)
X
e
don鈥檛 care
Order Number DP8480AJ or DP8480AN
See NS Package Number J16A or N16A
TL F 5861 鈥?1
Top View
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 5861
RRD-B30M105 Printed in U S A

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