DP8459V-25NS Datasheet

IC型號(hào)：
DP8459V-25NS
PDF描述：
All-Code Data Synchronizer
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NSC

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DP8459 All-Code Data Synchronizer

DP8459

ADVANCED

December 1995

DP8459 All-Code Data Synchronizer

General Description

The DP8459 Data Synchronizer is an integrated phase

locked loop circuit which has been designed for application

in magnetic hard disk, 鏗俥xible (鏗俹ppy) disk, optical disk, and

tape drive memory systems for data re-synchronization and

clock recovery with any standard recording code, operating

to 25 Mb/s. The DP8459 is provided in a 28-pin PCC

package. Zero phase start is employed during both data and

reference clock lock sequences for rapid acquisition. An

optional

(Customer-controlled)

synchronization

鏗乪ld

frequency-acquisition feature guarantees lock, accommo-

dating the preamble types used with GCR (Group Code

Recording), MFM (Modi鏗乪d Frequency Modulation), the

[1,N] run length limited (RLL) codes, and either of the

standard 2,7 RLL codes. Precise synchronization window

generation is achieved via an internal, self-aligning delay line

which remains accurate independent of temperature, power

supply, external component and IC process variations. The

DP8459 also incorporates a digitally controlled ( MICROW-

IRE

鈩?/div>

bus compatible) strobe function with 5-bit resolution

which allows for margin testing, error recovery routines, and

precise window calibration. The PLL 鏗乴ter resides external to

the chip, with two ports provided to allow signi鏗乧ant design

鏗俥xibility. Synchronization pattern detection circuitry issues a

PREAMBLE DETECTED signal when a pre-determined

length of the user-selected pattern is encountered. All digital

input and output signals are TTL compatible and a single,

+5V power supply is required. The DP8459V is offered as a

DP8459V-10 (250 Kbit/sec thru 10 Mbits/sec) or

DP8459V-25 (250 Kbits/sec thru 25 Mbit/sec), see AC

Electrical Characteristics.

Features

Fully integrated dual-gain PLL

Zero phase start lock sequence

250 Kbit/sec鈥?5 Mbit/sec data rate range

Frequency lock capability (optional) for all standard

recording codes

Digital window strobe control, 5-bit resolution

Two-port PLL 鏗乴ter network

PLL free-run (Coast) control for optical disk defects

Synchronization pattern (preamble lock) detection

Non-glitching multiplexed read/write clock output

+5V supply

DP8459 supplied in 28-pin plastic chip carrier (PCC)

and 40-pin TapePak packages

Connection Diagrams

TL/F/9322-6

FIGURE 1. DP8459 in 28-Pin Plastic Chip Carrier (PCC) V-Type Package Order Number DP8459V-10 or DP8459V-25

TapePak

廬

is a registered trademark of National Semiconductor Corporation.

MICROWIRE

鈩?/div>

is a trademark of National Semiconductor Corporation.

漏 1996 National Semiconductor Corporation

TL/F/9322

http:\\www.national.com

PrintDate=1996/07/31 PrintTime=11:05:38 ds009322 Rev. No. 1

Proof

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DP8459V-25NS Datasheet

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