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DP8440 Datasheet

  • DP8440

  • 46頁

  • ETC

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DP8440-40 DP8440-25 DP8441-40 DP8441-25 microCMOS Programmable 16 64 Mbit
Dynamic RAM Controller Driver
February 1995
DP8440-40 DP8440-25 DP8441-40 DP8441-25
microCMOS Programmable 16 64 Mbit
Dynamic RAM Controller Driver
General Description
The DP8440 41 Dynamic RAM Controllers provide an easy
interface between dynamic RAM arrays and 8- 16- 32- and
64-bit microprocessors The DP8440 41 DRAM Controllers
generate all necessary control and timing signals to suc-
cessfully interface and design dynamic memory systems
With significant enhancements over the DP8420 21 22
predecessors the DP8440 41 are suitable for high perform-
ance memory systems These controllers support page and
burst accesses for fast page static column and nibble
DRAMs Refreshes and accesses are arbitrated on chip
RAS low time during refresh and RAS precharge time are
guaranteed by these controllers Separate precharge coun-
ters for each RAS output avoid delayed back to back ac-
cesses due to precharge when using memory interleaving
Programmable features make the DP8440 41 DRAM Con-
trollers flexible enough to fit many memory systems
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
40 MHz and 25 MHz operation
Page detection
Automatic CPU burst accesses
Support 1 4 16 64 Mbits DRAMs
High capacitance drivers for RAS CAS WE and Q out-
puts
Support for fast page static column and nibble mode
DRAMs
High precision PLL based delay line
Byte enable for word size up to 32 bits on the DP8440
or 64 bits on the DP8441
Automatic Internal Refresh
Staggered RAS-Only refresh
Burst and CAS-before-RAS refresh
Error scrubbing during refresh
TRI-STATE outputs
Easy interface to all major microprocessors
Block Diagram
TL F 11718 鈥?1
FIGURE 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 11718
RRD-B30M75 Printed in U S A

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