DP8392A NS32492A Coaxial Transceiver Interface
May 1988
DP8392A NS32492A Coaxial Transceiver Interface
General Description
The DP8392A Coaxial Transceiver Interface (CTI) is a coax-
ial cable line driver receiver for Ethernet Thin Ethernet
(Cheapernet) type local area networks The CTI is connect-
ed between the coaxial cable and the Data Terminal Equip-
ment (DTE) In Ethernet applications the transceiver is usu-
ally mounted within a dedicated enclosure and is connected
to the DTE via a transceiver cable In Cheapernet applica-
tions the CTI is typically located within the DTE and con-
nects to the DTE through isolation transformers only The
CTI consists of a Receiver Transmitter Collision Detector
and a Jabber Timer The Transmitter connects directly to a
50 ohm coaxial cable where it is used to drive the coax
when transmitting During transmission a jabber timer is ini-
tiated to disable the CTI transmitter in the event of a longer
than legal length data packet Collision Detection circuitry
monitors the signals on the coax to determine the presence
of colliding packets and signals the DTE in the event of a
collision
The CTI is part of a three chip set that implements the com-
plete IEEE 802 3 compatible network node electronics as
shown below The other two chips are the DP8391 Serial
Network Interface (SNI) and the DP8390 Network Interface
Controller (NIC)
The SNI provides the Manchester encoding and decoding
functions whereas the NIC handles the Media Access Pro-
tocol and the buffer management tasks Isolation between
the CTI and the SNI is an IEEE 802 3 requirement that can
be easily satisfied on signal lines using a set of pulse trans-
formers that come in a standard DIP However the power
isolation for the CTI is done by DC-to-DC conversion
through a power transformer
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Compatible with Ethernet II IEEE 802 3 10Base5 and
10Base2 (Cheapernet)
Integrates all transceiver electronics except signal
power isolation
Innovative design minimizes external component count
Jabber timer function integrated on chip
Externally selectable CD Heartbeat allows operation
with IEEE 802 3 compatible repeaters
Precision circuitry implements receive mode collision
detection
Squelch circuitry at all inputs rejects noise
Designed for rigorous reliability requirements of
IEEE 802 3
Standard Outline 16-pin DIP uses a special leadframe
that significantly reduces the operating die temperature
Table of Contents
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System Diagram
Block Diagram
Functional Description
Receiver and Squelch
Transmitter and Squelch
Collision and Heartbeat
Jabber Timer
Connection Diagram
Pin Descriptions
Absolute Maximum Ratings
Electrical Characteristics
Switching Characteristics
Timing and Load Diagram
Physical Dimensions
1 0 System Diagram
TL F 7405 鈥?1
IEEE 802 3 Compatible Ethernet Cheapernet Local Area Network Chip Set
C
1995 National Semiconductor Corporation
TL F 7405
RRD-B30M105 Printed in U S A
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