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DP83865DVH Datasheet

  • DP83865DVH

  • DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer

  • 589.60KB

  • 86頁

  • NSC

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DP83865 Gig PHYTER廬 V 10/100/1000 Ethernet Physical Layer
October 2004
DP83865 Gig PHYTER
廬
V
10/100/1000 Ethernet Physical Layer
General Description
The DP83865 is a fully featured Physical Layer transceiver
with integrated PMD sublayers to support 10BASE-T,
100BASE-TX and 1000BASE-T Ethernet protocols.
The DP83865 is an ultra low power version of the DP83861
and DP83891. It uses advanced 0.18 um, 1.8 V CMOS
technology, fabricated at National Semiconductor鈥檚 South
Portland, Maine facility.
The DP83865 is designed for easy implementation of
10/100/1000 Mb/s Ethernet LANs. It interfaces directly to
Twisted Pair media via an external transformer. This device
interfaces directly to the MAC layer through the IEEE
802.3u Standard Media Independent Interface (MII), the
IEEE 802.3z Gigabit Media Independent Interface (GMII),
or Reduced GMII (RGMII).
The DP83865 is a fourth generation Gigabit PHY with field
proven architecture and performance. Its robust perfor-
mance ensures drop-in replacement of existing
10/100 Mbps equipment with ten to one hundred times the
performance using the existing networking infrastructure.
鈻?/div>
Integrated PMD sublayer featuring adaptive equalization
and baseline wander compensation according to ANSI
X3.T12
鈻?/div>
3.3 V or 2.5 V MAC interfaces:
鈻?/div>
IEEE 802.3u MII
鈻?/div>
IEEE 802.3z GMII
鈻?/div>
RGMII version 1.3
鈻?/div>
User programmable GMII pin ordering
鈻?/div>
IEEE 802.3u Auto-Negotiation and Parallel Detection
鈻?/div>
Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s,
and 10 Mb/s full duplex and half duplex devices
鈻?/div>
Speed Fallback mode to achieve quality link
鈻?/div>
Cable length estimator
鈻?/div>
LED support for activity, full / half duplex, link1000,
Applications
The DP83865 fits applications in:
鈻?/div>
10/100/1000 Mb/s capable node cards
鈻?/div>
Switches with 10/100/1000 Mb/s capable ports
鈻?/div>
High speed uplink ports (backbone)
link100 and link10, user programmable (manual on/off),
or reduced LED mode
鈻?/div>
Supports 25 MHz operation with crystal or oscillator.
鈻?/div>
Requires only two power supplies, 1.8 V (core and
analog) and 2.5 V (analog and I/O). 3.3V is supported
as an alternative supply for I/O voltage
鈻?/div>
User programable interrupt
鈻?/div>
Supports Auto-MDIX at 10, 100 and 1000 Mb/s
鈻?/div>
Supports JTAG (IEEE1149.1)
鈻?/div>
128-pin PQFP package (14mm x 20mm)
Features
鈻?/div>
Ultra low power consumption typically 1.1 watt
鈻?/div>
Fully compliant with IEEE 802.3 10BASE-T, 100BASE-
TX and 1000BASE-T specifications
SYSTEM DIAGRAM
MII
GMII
RGMII
10BASE-T
100BASE-TX
1000BASE-T
RJ-45
DP83820
10/100/1000 Mb/s
ETHERNET MAC
DP83865
10/100/1000 Mb/s
ETHERNET PHYSICAL LAYER
25 MHz
crystal or oscillator
STATUS
LEDs
PHYTER廬 is a registered trademark of National Semiconductor Corporation
漏 2004 National Semiconductor Corporation
MAGNETICS
www.national.com

DP83865DVH 產(chǎn)品屬性

  • National Semiconductor (TI)

  • Tray

  • 66

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