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DP83843BVJE Datasheet

  • DP83843BVJE

  • PHYTER

  • 87頁(yè)

  • NSC

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DP83843BVJE PHYTER
July 1999
DP83843BVJE PHYTER
General Description
Features
The DP83843BVJE is a full feature Physical Layer device 鈥?IEEE 802.3 ENDEC with AUI/10BASE-T transceivers
with integrated PMD sublayers to support both 10BASE-T
and built-in filters
and 100BASE-X Ethernet protocols.
鈥?IEEE 802.3u 100BASE-TX compatible - directly drives
standard Category 5 UTP, no need for external
This VLSI device is designed for easy implementation of
100BASE-TX transceiver
10/100 Mb/s Ethernet LANs. It interfaces directly to Twisted
Pair media through an external transformer or to 鏗乥er 鈥?Fully Integrated and fully compliant ANSI X3.263 TP-
media via industry standard electrical/optical 鏗乥er PMD
PMD physical sublayer which includes adaptive equal-
transceivers. This device also interfaces directly to the
ization and BLW compensation
MAC layer through the IEEE 802.3u standard Media Inde-
鈥?IEEE 802.3u 100BASE-FX compatible - connects direct-
pendent Interface (MII), ensuring interoperability between
ly to industry standard Electrical/Optical transceivers
products from different vendors.
鈥?IEEE 802.3u Auto-Negotiation for automatic speed se-
The DP83843 is designed with National Semiconductor's
lection
advanced CMOS process. Its system architecture is based
on the integration of several of National's industry proven 鈥?IEEE 802.3u compatible Media Independent Interface
(MII) with Serial Management Interface
core technologies:
鈥?Integrated high performance 100 Mb/s clock recovery
鈥?IEEE 802.3 ENDEC with AUI/10BASE-T transceiver
circuitry requiring no external filters
module to provide the 10 Mb/s functions
鈥?Clock Recovery/Generator Modules from National's Fast 鈥?Full Duplex support for 10 and 100 Mb/s data rates
鈥?MII Serial 10 Mb/s mode
Ethernet and FDDI products
鈥?Fully configurable node/switch and 100Mb/s repeater
鈥?FDDI Stream Cipher scrambler/descrambler for
modes
TP-PMD
鈥?100BASE-X physical coding sub-layer (PCS) and control 鈥?Programmable loopback modes for flexible system diag-
nostics
logic that integrates the core modules into a dual speed
Ethernet physical layer controller
鈥?Flexible LED support
鈥?ANSI X3T12 Compliant TP-PMD Transceiver
鈥?Single register access to complete PHY status
technology with Baseline Wander (BLW) compensation
鈥?MDIO interrupt support
鈥?Individualized scrambler seed for 100BASE-TX applica-
tions using multiple PHYs
鈥?Low power consumption for multi-port applications
鈥?Small footprint 80-pin PQFP package
System Diagram
MII
10 AND/OR 100 Mb/s
ETHERNET MAC OR
100Mb/s REPEATER
CONTROLLER
MAGNETICS
10BASE-T or
100BASE-TX
DP83843
10/100 Mb/s
ETHERNET PHYSICAL LAYER
RJ-45
10BASE-T
or
100BASE-TX
25 MHz
CLOCK
STATUS
LEDS
100BASE-FX/
AUI
ThunderLAN
廬
is a registered trademark of Texas Instruments.
TWISTER鈩?is a trademark of National Semiconductor Corporation.
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏
1999 National Semiconductor Corporation
www.national.com

DP83843BVJE 產(chǎn)品屬性

  • National Semiconductor (TI)

  • Tray

  • 84

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