DP83816 Datasheet

IC型號：
DP83816
PDF描述：
DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access Con...
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DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPHYTER-II鈩?

June 2003

DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access

Controller and Physical Layer (MacPHYTER-II

鈩?/div>

)

General Description

鈥?Support for IEEE 802.3x Full duplex flow control

鈥?Extremely flexible Rx packet filtration including: single

DP83816 is a single-chip 10/100 Mb/s Ethernet Controller

address perfect filter with MSb masking, broadcast, 512

for the PCI bus. It is targeted at low-cost, high volume PC

entry multicast/unicast hash table, deep packet pattern

motherboards, adapter cards, and embedded systems.

matching for up to 4 unique patterns

The DP83816 fully implements the V2.2 33 MHz PCI bus

interface for host communications with power management 鈥?Statistics gathered for support of RFC 1213 (MIB II),

RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing

support. Packet descriptors and data are transferred via

CPU overhead for management

bus-mastering, reducing the burden on the host CPU. The

DP83816 can support full duplex 10/100 Mb/s transmission 鈥?Internal 2 KB Transmit and 2 KB Receive data FIFOs

and reception, with minimum interframe gap.

鈥?Serial EEPROM port with auto-load of configuration data

The DP83816 device is an integration of an enhanced

from EEPROM at power-on

version of the National Semiconductor PCI MAC/BIU 鈥?Flash/PROM interface for remote boot support

(Media Access Controller/Bus Interface Unit) and a 3.3V

鈥?Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical

CMOS physical layer interface.

layer

Features

鈥?IEEE 802.3 10BASE-T transceiver with integrated filters

鈥?IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports 鈥?IEEE 802.3u 100BASE-TX transceiver

traditional data rates of 10 Mb/s Ethernet and 100 Mb/s 鈥?Fully integrated ANSI X3.263 compliant TP-PMD

Fast Ethernet (via internal phy)

physical sublayer with adaptive equalization and

Baseline Wander compensation

鈥?Bus master - burst sizes of up to 128 dwords (512 bytes)

鈥?BIU compliant with PC 97 and PC 98 Hardware Design 鈥?IEEE 802.3u Auto-Negotiation - advertised features

configurable via EEPROM

Guides, PC 99 Hardware Design Guide draft, ACPI v1.0,

PCI Power Management Specification v1.1, OnNow 鈥?Full Duplex support for 10 and 100 Mb/s data rates

Device Class Power Management Reference

鈥?Single 25 MHz reference clock

Specification - Network Device Class v1.0a

鈥?Wake on LAN (WOL) support compliant with PC98, 鈥?144-pin LQFP package

PC99, SecureOn, and OnNow, including directed 鈥?Low power 3.3V CMOS design with typical consumption

of 383 mW operating, 297 mW during WOL and 53 mW

packets, Magic Packet餂? VLAN packets, ARP packets,

during sleep mode

pattern match packets, and Phy status change

鈥?IEEE 802.3u MII for connecting alternative external

鈥?Clkrun function for PCI Mobile Design Guide

Physical Layer Devices

鈥?Virtual LAN (VLAN) and long frame support

鈥?3.3V signalling with 5V tolerant I/O.

System Diagram

PCI Bus

10/100 Twisted Pair

DP83816

Isolation

BIOS ROM EEPROM

(optional) (optional)

TRI-STATE

廬

is a registered trademark of National Semiconductor Corporation.

MacPHYTER-II餂?is a trademark of National Semiconductor Corporation.

Magic Packet餂?is a trademark of Advanced Micro Devices, Inc.

漏

2003 National Semiconductor Corporation

www.national.com

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