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DP5Z2MW32PV320C Datasheet

  • DP5Z2MW32PV320C

  • x32 Flash EEPROM Module

  • 692.62KB

  • 18頁(yè)

  • ETC

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64 Megabit FLASH EEPROM
PRELIMINARY
DESCRIPTION:
The DP5Z2MW32PV3 鈥樷€橵ERSA-STACK鈥欌€?module is a revolutionary new
memory subsystem using Dense-Pac Microsystems鈥?ceramic Stackable
Leadless Chip Carriers (SLCC) mounted on a co-fired ceramic substrate. It
offers 64 Megabits of FLASH EEPROM in a single package envelope of 1.090"
x 1.090" x .252".
The DP5Z2MW32PV3 is built with two stacks of 2 SLCC packages each
containing a 1Meg x 16 FLASH memory devices. Each SLCC is hermetically
sealed making the module suitable for commercial, industrial and military
applications.
By using SLCCs, the 鈥樷€橵ersa-Stack鈥欌€?family of modules offers a higher board
density of memory than available with conventional through-hole, surface
mount, module or hybrid techniques.
DP5Z2MW32PV3
PIN NAMES
FEATURES:
鈥?/div>
Organizations Available: 2 Meg x 32, 4 Meg x 16
鈥?/div>
Fast Access Times: 120, 150, 200ns (max.)
鈥?/div>
Single 5.0 Volt
鈥?/div>
High-Density Symmetrically Blocked Architecture
- Sixteen 128 Kbyte Blocks Per Device
A0 - A19
I/O0 - I/O31
CE0 - CE3
WE
OE
V
DD
V
SS
N.C.
Address Inputs
Data Input/Output
Chip Enables
Write Enables
Output Enables
Power (+5 Volts)
Ground
No Connect
鈥?/div>
Extended Cycling Capability
- 100K Write/Erase Cycles
鈥?/div>
Automated Erase and Program Cycles
- Command User Interface
- Status Register
FUNCTIONAL BLOCK DIAGRAM
鈥?/div>
SRAM-Compatible Write Interface
鈥?/div>
Hardware Data Protection Feature
- Erase / Write Lockout during
Power Transitions
鈥?/div>
66 - Pin PGA 鈥樷€橵ERSA-STACK鈥欌€?Package
PIN-OUT DIAGRAM
30A180-12
Rev. C
This document contains information on a product presently under
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1

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