DM74LS962 (DM86LS62) Dual Rank 8-Bit TRI-STATE Shift Register
August 1991
DM74LS962 (DM86LS62)
Dual Rank 8-Bit TRI-STATE Shift Register
General Description
These circuits are TRI-STATE edge-triggered 8-bit I O reg-
isters in parallel with 8-bit serial shift registers which are
capable of operating in any of the following modes parallel
load from I O pins to register 鈥樷€楢鈥欌€?parallel transfer down
from register 鈥樷€楢鈥欌€?to serial shift register 鈥樷€楤鈥欌€?parallel transfer
up from shift register 鈥樷€楤鈥欌€?to register 鈥樷€楢鈥欌€?serial shift of regis-
ter 鈥樷€楤鈥欌€?or exchange data between register 鈥樷€楢鈥欌€?and shift
register 鈥樷€楤鈥欌€?Since the registers are edge-triggered by the
positive transition of the clock the control lines which deter-
mine the mode or operation are completely independent of
the logic level applied to the clock Designed for bus-orient-
ed systems these circuits have their TRI-STATE inputs and
outputs on the same pins
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Registers are edge-triggered by the positive transition
of the clock
All inputs are PNP transistors
Input disable dominates over output disable
Output high impedance state does not impede any oth-
er mode of operation
8-bit I O pins are TRI-STATE buffers
Typical shift frequency is 36 MHz
Typical power dissipation is 305 mW
All control inputs are active when in an 鈥樷€楲鈥欌€?logic state
Devices can be cascaded into N-bit word
Connection Diagram
Dual-In-Line Package
Pin Description
DIS
O
Output disable
I
S
Serial input
DIS
I
Input disable
DIS
TU
Transfer up disable
DIS
TD
Transfer down disable
DIS
S
Shift disable
O
S
Serial output
CLK Clock
GND Ground
I O1
I O 8 8-bit I O pins
V
CC
Supply Voltage
TL F 6438 鈥?1
Top View
Order Number DM74LS962N or DM86LS62N
See NS Package Number N18A
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 6438
RRD-B30M105 Printed in U S A
1
2
3
4
5
6
7
8
