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DM7556J Datasheet

  • DM7556J

  • TRI-STATE? Programmable Binary Counters

  • 8頁

  • NSC

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DM7556 DM8556 TRI-STATE Programmable Binary Counters
August 1989
DM7556 DM8556 TRI-STATE Programmable
Binary Counters
General Description
These circuits are synchronous edge-sensitive fully-pro-
grammable 4-bit counters The counters feature both con-
ventional totem-pole and TRI-STATE outputs such that
when the outputs are in the high impedance mode they can
be used to enter data from the bus lines In addition the
clear input operates completely independent of all other in-
puts During the programming operation data is loaded into
the flip-flops on the positive-going edge of the clock pulse
To facilitate cascading of these counters the MAX COUNT
output can be tied directly into the count enable input of the
next counter
Features
Y
Y
Y
Y
Y
Typical clock frequency 35 MHz
TRI-STATE outputs
Fully independent clear
Synchronous loading
Cascading circuitry provided internally
Connection Diagram
Dual-In-Line Package
TL F 6588 鈥?1
Order Number DM7556J or DM8556N
See NS Package Number J16A or N16A
Function Table
Control Inputs
LOAD
H
H
H
H
L
H
H
CE
X
X
X
X
H
L
L
CLK
X
X
L
L
OD
L
H
L
H
L
L
H
Reset
H
H
L
L
L
L
L
I O
A
L
Z
Q
A0
Z
a
Z
I O Ports
I O
B
I O
C
I O
D
L
Z
Q
D0
Z
d
Z
Q
A
L
L
Q
A0
Q
A0
A
Active Outputs
Q
B
Q
C
Q
D
L
L
Q
D0
Q
D0
D
u
u
u
L
L
Z
Z
Q
B0
Q
C0
Z
Z
b
c
COUNT
Z
Z
L
L
L
L
Q
B0
Q
C0
Q
B0
Q
C0
B
C
COUNT
COUNT
The I O pins are used as inputs when they are TRI-STATED and the LOAD input is Low They are outputs and active
when LOAD input is High and OD is Low
H
e
High Level (Steady State)
L
e
Low Level (Steady State)
X
e
Don鈥檛 Care including transitions
a b c d
e
The level of the steady state input at inputs A B C D respectively
Q
A0
Q
B0
Q
C0
Q
D0
e
The level of Q
A
Q
B
Q
C
Q
D
respectively before the indicated steady state input conditions
were established
TRI-STATE is a registered trademark of the National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 6588
RRD-B30M105 Printed in U S A

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