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DM74S74M Datasheet

  • DM74S74M

  • Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear...

  • 53.86KB

  • 5頁

  • FAIRCHILD

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DM74S74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs
August 1986
Revised April 2000
DM74S74
Dual Positive-Edge-Triggered D Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs. The infor-
mation on the D input is accepted by the flip-flops on the
positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the preset
or clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Order Number
DM74S74M
DM74S74N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Inputs
PR
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
鈫?/div>
鈫?/div>
L
D
X
X
X
H
L
X
Q
H
L
H*
H
L
Q
0
Outputs
Q
L
H
H*
L
H
Q
0
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
L
=
LOW Logic Level
鈫?=
Positive-going Transition
*
=
This configuration is nonstable; that is, it will not persist when either the
preset and/or clear inputs return to its inactive (HIGH) level.
Q
0
=
The output logic level of Q before the indicated input conditions were
established.
漏 2000 Fairchild Semiconductor Corporation
DS006457
www.fairchildsemi.com

DM74S74M 產(chǎn)品屬性

  • Fairchild Semiconductor

  • 2

  • DM74

  • D-Type Flip-Flop

  • Inverting/Non-Inverting

  • Single-Ended

  • 14 ns

  • - 1 mA

  • 5.25 V

  • + 70 C

  • SMD/SMT

  • SOIC-14

  • Rail

  • 0 C

  • 1

  • 1

  • 4.75 V

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