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DM74AS74SJX Datasheet

  • DM74AS74SJX

  • Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset an...

  • 7頁

  • FAIRCHILD

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DM74AS74 Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear
April 1984
Revised March 2000
DM74AS74
Dual D-Type Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The AS74 is a dual edge-triggered flip-flops. Each flip-flop
has individual D, clock, clear and preset inputs, and also
complementary Q and Q outputs.
Information at input D is transferred to the Q output on the
positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the D input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of LOW level sig-
nal.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
s
Improved AC performance over S74 at approximately
half the power
Ordering Code:
Order Number
DM74AS74M
DM74AS74SJX
DM74AS74N
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Inputs
PR
L
H
L
H
H
H
CLR CLK
H
L
L
H
H
H
X
X
X
鈫?/div>
鈫?/div>
L
D
X
X
X
H
L
X
Q
H
L
H (Note 1)
H
L
Q
0
Outputs
Q
L
H
H (Note 1)
L
H
Q
0
L
=
LOW State
H
=
HIGH State
X
=
Don't Care
鈫?=
Positive Edge Transition
Q
0
=
Previous Condition of Q
Note 1:
This condition is nonstable; it will not persist when preset and clear
inputs return to their inactive (HIGH) level. The output levels in this condi-
tion are not guaranteed to meet the V
OH
specification.
漏 2000 Fairchild Semiconductor Corporation
DS006282
www.fairchildsemi.com

DM74AS74SJX 產(chǎn)品屬性

  • 2,000

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74AS

  • 設(shè)置（預(yù)設(shè)）和復(fù)位

  • D 型

  • 差分

  • 2

  • 1

  • 105MHz

  • 3.5ns

  • 正邊沿

  • 2mA，20mA

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 14-SOIC（0.209"，5.30mm 寬）

  • 帶卷 (TR)

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