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DM74AS286M Datasheet

  • DM74AS286M

  • 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Po...

  • 67.89KB

  • 7頁

  • FAIRCHILD

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DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port
October 1986
Revised April 2000
DM74AS286
9-Bit Parity Generator/Checker
with Bus-Driver Parity I/O Port
General Description
These universal, 9-bit parity generators/checkers utilize
advanced Schottky high performance circuitry and feature
odd/even outputs to facilitate operation of either odd or
even parity applications. The word length capability is eas-
ily expanded by cascading.
The DM74AS286 can be used to upgrade the performance
of most systems utilizing the DM74AS280 parity generator/
checker. Although the DM74AS286 is implemented without
expander inputs, the corresponding function is provided by
the availability of an input pin XMIT. XMIT is a control line
which makes parity error output active and parity an input
port when HIGH; when LOW, parity error output is inactive
and parity becomes an output port. In addition, parity I/O
control circuitry contains a feature to keep the I/O port in
the 3-STATE during power UP or DOWN to prevent bus
glitches.
Features
s
PNP inputs to reduce bus loading
s
Generates either odd or even parity for nine data lines
s
Inputs are buffered to lower the drive requirements
s
Can be used to upgrade existing systems using MSI
parity circuits
s
Cascadable for n-bits
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full
temperature and V
CC
range
s
A parity I/O portable to drive bus
Ordering Code:
Order Number
DM74AS286M
DM74AS286N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Number of Inputs
(A thru I)
that are HIGH
0, 2, 4, 6, 8
1, 3, 5, 7, 9
0, 2, 4, 6, 8
0, 2, 4, 6, 8
1, 3, 5, 7, 9
1, 3, 5, 7, 9
L
=
LOW Logic Level
H
=
HIGH Logic Level
N/A
=
Not Applicable
Parity I/O
Input Output
N/A
N/A
H
L
H
L
H
L
N/A
N/A
N/A
N/A
Parity
XMIT Error
L
L
H
H
H
H
H
H
H
L
L
H
Mode
of
Operation
Parity
Generator
Parity
Checker
Parity
Checker
漏 2000 Fairchild Semiconductor Corporation
DS006305
www.fairchildsemi.com

DM74AS286M 產(chǎn)品屬性

  • 55

  • 集成電路 (IC)

  • 邏輯 - 奇偶校驗發(fā)生器和校驗器

  • 74AS

  • 奇偶校驗發(fā)生器/校驗器

  • 9 位

  • 15mA，48mA; 2mA，20mA

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 14-SOIC（0.154"，3.90mm 寬）

  • 14-SOIC

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