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DM74ALS541WM Datasheet

  • DM74ALS541WM

  • Octal Buffer and Line Driver with 3-STATE Outputs

  • 65.59KB

  • 6頁

  • FAIRCHILD

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DM74ALS541 Octal Buffer and Line Driver with 3-STATE Outputs
October 1986
Revised February 2000
DM74ALS541
Octal Buffer and Line Driver with 3-STATE Outputs
General Description
This octal buffer and line driver is designed to have the per-
formance of the DM74ALS240A series and, at the same
time, offer a pinout with inputs and outputs on opposite
sides of the package. This arrangement greatly enhances
circuit board layout. The 3-STATE control gate is a 2-input
NOR such that if either G1 or G2 is HIGH, all eight outputs
are in the high impedance state.
Features
s
Advanced oxide-isolated ion-implanted Schottky TTL
process
s
Switching performance is guaranteed over full tempera-
ture and V
CC
supply range
s
Data flow-thru pinout (all inputs on opposite side from
outputs)
s
P-N-P Inputs reduce DC loading
Ordering Code:
Order Number
DM74ALS541WM
DM74ALS541SJ
DM74ALS541N
Package Number Package Description
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Input
G1
H
X
L
L
G2
X
H
L
L
A
X
X
L
H
Output
Y
Hi-Z
Hi-Z
L
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don't Care (Either LOW or HIGH Logic Level)
Hi-Z
=
High Impedance (OFF) State
漏 2000 Fairchild Semiconductor Corporation
DS009171
www.fairchildsemi.com

DM74ALS541WM 產(chǎn)品屬性

  • 36

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅動器，接收器，收發(fā)器

  • 74ALS

  • 緩沖器/線路驅動器，非反相

  • 1

  • 8

  • 15mA，24mA

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 20-SOIC（0.295"，7.50mm 寬）

  • 20-SOIC

  • 管件

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