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DM74ALS5245WM Datasheet

  • DM74ALS5245WM

  • Octal 3-STATE Transceiver

  • 7頁

  • FAIRCHILD

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DM74ALS5245 Octal 3-STATE Transceiver
October 1986
Revised February 2000
DM74ALS5245
Octal 3-STATE Transceiver
General Description
This octal bus transceiver is designed for asynchronous
two-way communication between data buses. The inputs
include hysteresis which provides improved noise rejec-
tion. Data is transmitted either from the A bus to the B bus
or from the B bus to the A bus depending on the logic level
of the direction control (DIR) input. The device can be dis-
abled via the enable input (G) which causes the outputs to
enter the high impedance mode so the buses are effec-
tively isolated.
Features
s
Input Hysteresis
s
Low output noise generation
s
High input noise immunity
s
Advanced oxide-isolated, ion implanted Schottky TTL
process
s
Switching specification guaranteed over the full temper-
ature and V
CC
range
s
PNP inputs to reduce input loading
Ordering Code:
Order Number
DM74ALS5245WM
DM74ALS5245SJ
DM74ALS5245N
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Control Inputs
Operation
G
L
L
H
L
=
LOW Logic Level
DIR
L
H
X
H
=
HIGH Logic Level
B Data to A Bus
A Data to B Bus
High Impedance
X
=
Don't Care (Either LOW or HIGH Logic Level)
漏 2000 Fairchild Semiconductor Corporation
DS009175
www.fairchildsemi.com

DM74ALS5245WM 產(chǎn)品屬性

  • 36

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 74ALS

  • 收發(fā)器，非反相

  • 1

  • 8

  • 15mA，24mA

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 20-SOIC（0.295"，7.50mm 寬）

  • 20-SOIC

  • 管件

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