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DM74ALS521WM Datasheet

  • DM74ALS521WM

  • 8-Bit Comparator

  • 5頁

  • FAIRCHILD

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DM74ALS520 鈥?DM74ALS521 8-Bit Comparator
September 1986
Revised April 2000
DM74ALS520 鈥?DM74ALS521
8-Bit Comparator
General Description
These comparators perform an 鈥渆qual to鈥?comparison of
two 8-bit words with provision for expansion or external
enabling. The matching of the two 8-bit input plus a logic
LOW on the EN input produces the output A
=
B on the
DM74ALS520 and DM74ALS521. The DM74ALS520 and
DM74ALS521 have totem pole outputs for wire AND cas-
cading. Additionally, the DM74ALS520 is provided with B
input pull up termination resistors for analog or switch data.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Functionally and pin for pin compatible with LS family
counterpart
s
Improved output transient handling capability
Ordering Code:
Ordering Code
DM74ALS520WM
DM74ALS520N
DM74ALS521WM
SM74ALS521N
Package Number
M20B
N20A
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Inputs
EN
L
L
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don't Care
Output
Data
A
=
B
A
鈮?/div>
B
X
A
=
B
L
H
H
漏 2000 Fairchild Semiconductor Corporation
DS006114
www.fairchildsemi.com

DM74ALS521WM 產(chǎn)品屬性

  • 36

  • 集成電路 (IC)

  • 邏輯 - 比較器

  • 74ALS

  • 身份比較器

  • 8

  • 低有效

  • A=B

  • 4.5 V ~ 5.5 V

  • 2.6mA，24mA

  • 20ns @ 4.5V ~ 5.5V，50pF

  • -

  • 0°C ~ 70°C

  • 20-SOIC（0.295"，7.50mm 寬）

  • 表面貼裝

  • 管件

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