DM74ALS165 8-Bit Parallel In/Serial Out Shift Register
January 1986
Revised February 2000
DM74ALS165
8-Bit Parallel In/Serial Out Shift Register
General Description
The DM74ALS165 is an 8-bit serial register that, when
clocked, shifts the data toward serial output, Q
H
. Parallel-in
access to each stage is provided by eight individual direct
data inputs that are enabled by a low level at the SH/LD
input. The DM74ALS165 also features a clock inhibit func-
tion and a complemented serial output, Q
H
.
Clocking is accomplished by a LOW-to-HIGH transition of
the CLK input while SH/LD is held HIGH and CLK INH is
held LOW. The functions of the CLK and CLK INH (clock
inhibit) inputs are interchangeable. Since a LOW CLK input
and a LOW-to-HIGH transition of CLK INH will also accom-
plish clocking, CLK INH should be changed to the high
level only while the CLK input is HIGH. Parallel loading is
inhibited when SH/LD is held HIGH. The parallel inputs to
the register are enabled while SH/LD is LOW indepen-
dently of the levels of CLK, CLK INH, or SER inputs.
Features
s
Complementary outputs
s
Direct overriding load (data) inputs
s
Gated clock inputs
s
Parallel-to-serial data conversion
Ordering Code:
Order Number
DM74ALS165M
DM74ALS165N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Inputs
Shift/ Clock Clock Serial Parallel
Load Inhibit
L
H
H
H
H
H
H
X
L
L
L
鈫?/div>
鈫?/div>
H
X
L
鈫?/div>
鈫?/div>
L
L
X
X
X
H
L
H
L
X
A...H
a...h
X
X
X
X
X
X
Internal
Outputs
Q
A
a
Q
A0
H
L
H
L
Q
A0
Q
B
b
Q
B0
Q
An
Q
An
Q
An
Q
An
Q
B0
Output
Q
H
h
Q
H0
Q
Gn
Q
Gn
Q
Gn
Q
Gn
Q
H0
H
=
HIGH Level (steady-state),
L
=
LOW Level (steady-state)
X
=
Don't Care (any input, including transitions)
鈫?=
Transition from LOW-to-HIGH level
a...h
=
The level of steady-state input at inputs A through H, respectively
Q
A0
, Q
B0
, Q
H0
=
The level of Q
A
, Q
B
, or Q
H
, respectively, before the
indicated steady-state input conditions were established
Q
An
, Q
Gn
=
The level of Q
A
or Q
G
, respectively, before the most recent
鈫?/div>
transition of the clock
漏 2000 Fairchild Semiconductor Corporation
DS006712
www.fairchildsemi.com
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