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DM74ALS125N Datasheet

  • DM74ALS125N

  • Quad 3-STATE Buffer

  • 5頁(yè)

  • FAIRCHILD

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DM74ALS125 Quad 3-STATE Buffer
November 1989
Revised February 2000
DM74ALS125
Quad 3-STATE Buffer
General Description
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the 3-STATE feature. The 3-STATE circuitry contains a fea-
ture that maintains the buffer outputs in 3-STATE (high
impedance state) during power supply ramp-up or ramp-
down. This eliminates bus glitching problems that arise
during power-up and power-down. To minimize the possi-
bility that two outputs will attempt to take a common bus to
opposite logic levels, the disable time is shorter than the
enable time of the outputs.
Features
s
Advanced low power
Schottky TTL process
oxide-isolated
ion-implanted
s
Functional and pin compatible with the 74LS counterpart
s
Switching response specified into 500鈩?and 50 pF load
s
Switching response specifications guaranteed over full
temperature and V
CC
supply range
s
PNP input design reduces input loading
s
Low level drive current: 74ALS
=
24 mA
Ordering Code:
Order Number
DM74ALS125M
DM74ALS125N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Logic Diagram
Functional Table
Y
=
A
Input
A
L
H
X
C
L
L
H
Output
Y
L
H
Hi-Z
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
Hi-Z
=
3-STATE (Outputs are disabled)
漏 2000 Fairchild Semiconductor Corporation
DS010620
www.fairchildsemi.com

DM74ALS125N 產(chǎn)品屬性

  • 500

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 74ALS

  • 緩沖器/線路驅(qū)動(dòng)器，非反相

  • 4

  • 1

  • 15mA，24mA

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 通孔

  • 14-DIP（0.300"，7.62mm）

  • 14-DIP

  • 管件

  • 74ALS125

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