Enhanced
Features
Memory Systems Inc.
DM512K32ST6/DM512K36ST6 Multibank EDO
512Kb x 32/512Kb x 36 EDRAM SIMM
Product Specification
Architecture
The DM512K36ST6
achieves 512K x 36 density by
Actives Pages (Multibank Cache)
s
Fast DRAM Array for 30ns Access to Any New Page
mounting five 512K x 8
s
Write Posting Register for 12ns Random Writes and Burst Writes
EDRAMs, packaged in 44-pin
Within a Page (Hit or Miss)
plastic TSOP-II packages, on a
s
1KByte Wide DRAM to SRAM Bus for 56.8 Gigabytes/Sec Cache Fill
multi-layer substrate. Four
s
On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
2203 devices and one
on Writes
DM2213 device provide data
s
EDO Mode for 83 MHz Non-Interleave Burst Rate
and parity storage. The
s
Hidden Precharge and Refresh Cycles
DM512K32 contains four
s
Extended 64ms Refresh Period for Low Standby Power
2203 devices for data only.
s
Standard CMOS/TTL Compatible I/O Levels and +5 Volt Supply
The EDRAM memory
s
Compatibility with JEDEC 512K x 32/36 DRAM SIMM Configuration
module architecture is very
Allows Performance Upgrade in System
similar to a standard 2MB
s
Industrial Temperature Range Option
DRAM module with the
addition of an integrated
Description
cache and on-chip control which allows it to operate much like a
The Enhanced Memory Systems 2MB EDRAM SIMM module
page mode or static column DRAM.
provides a single memory module solution for the main memory or
The EDRAM鈥檚 SRAM cache is integrated into the DRAM array as
local memory of fast embedded control, DSP, and other high
tightly coupled row registers. The 512K x 32/36 EDRAM SIMM has a
performance systems. Due to its fast 12ns cache row register, the
total of four independent DRAM memory banks each with its own 256
EDRAM memory module supports zero-wait-state burst read
operations at up to 83MHz bus rates in a non-interleave configuration x 32/36 SRAM row register. Memory reads always occur from the
cache row register of one of these banks as specified by row address
and >100MHz bus rates with a two-way interleave configuration.
bits A
8
and A
9
(bank select). When the internal comparator detects
On-chip write posting and fast page mode operation supports
that the row address matches the last row read from any of the four
12ns write and burst write operations. On a cache miss, the fast
DRAM array reloads the entire 1KByte cache over a 1KByte-wide bus DRAM banks (page hit), the SRAM is accessed and data is available
in 18ns for an effective bandwidth of 56.8 Gbytes/sec. This means
on the output pins in 12ns from column address input. Subsequent
very low latency and fewer wait states on a cache miss than a non-
reads within the page (burst reads or random reads) can continue at
integrated cache/DRAM solution. The JEDEC compatible 72-bit SIMM 12ns cycle time. When the row address does not match the last row
configuration allows a single memory controller to be designed to
read from any of the four DRAM banks (page miss), the new DRAM
support either JEDEC slow DRAMs or high speed EDRAMs to provide row is accessed and loaded into the appropriate SRAM row register
a simple upgrade path to higher system performance.
and data is available on the output pins
all within 30ns from row enable.
Subsequent reads within the page (burst
Functional Diagram
reads or random reads) can continue at
12ns cycle time. During either read hit or
/CAL
Column
0-3, P
A
0
- A
7
Address
read miss operations, the EDO option
Latch
Column Decoder
extends data output time to allow use of
4 - 256 X 36 Cache Pages
the full 83Mbyte/second bandwidth.
(Row Registers)
4 - 9 Bit
Comparators
Since reads occur from the SRAM
Sense Amps
cache, the DRAM precharge can occur
/G
& Column Write Select
A
0
- A
10
I/O
during burst reads. This eliminates the
4 - Last Row
Control
Read Address
DQ
0-35
and
precharge time delay suffered by other
Latches
Data
Latches
DRAMs and SDRAMs when accessing a
/S
new page. The EDRAM has an
Memory
Row
/WE
Array
Address
independent on-chip refresh counter and
2Mbyte + Parity
Latch
dedicated refresh control pin to allow the
DRAM array to be refreshed concurrently
with cache read operations (hidden
V
C
1-5
A
0
- A
9
V
refresh).
/F
Row Adress
s
4KByte SRAM Cache Memory for 12ns Random Reads Within Four
Row Decoder
CC
SS
W/R
/RE
0, 2
and
Refresh
Control
Refresh
Counter
The information contained herein is subject to change without notice. Enhanced reserves the
right to change or discontinue this product without notice.
漏 1996 Enhanced Memory Sytems Inc
, 1850 Ramtron Drive, Colorado Springs, CO
80921
Telephone
(800) 545-DRAM;
Fax
(719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2117-000
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