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DG507ABK Datasheet

  • DG507ABK

  • CMOS Analog Multiplexers

  • 607.20KB

  • 17頁

  • INTERSIL   INTERSIL

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P R OD U C T
O BSO LETE
P R OD U C T
UBSTITUTE LASTIC),
POSSIBLE S IP), DG406(P
RD
Data
ASTIC),
HI1-0506(CE
L
Sheet
IP), DG 407(P
RD
HI1-0507(CE
409
HI-0509 , DG
DG506A, DG507A, DG509A
May 2001
File Number
6010
CMOS Analog Multiplexers
itle
G50
,
507
A,
509
b-
t
MO
na-
lti-
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utho
)
ey-
rds
ter-
rpo-
ion,
i-
n-
ctor,
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x,
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OCI
The DG506A, DG507A and DG509A are CMOS Monolithic
16-Channel/Dual 8-Channel and Dual 4-Channel Analog
Multiplexers, which can also be used as demultiplexers. An
enable input is provided. When the enable input is high, a
channel is selected by the address inputs, and when low, all
channels are off.
A channel in the ON state conducts current equally well in
both directions. In the OFF state each channel blocks
voltages up to the supply rails. The address inputs and the
enable input are TTL and CMOS compatible over the full
specified operating temperature range.
The DG506A, DG507A and DG509A are pinout compatible
with the industry standard devices.
Features
鈥?Low Power Consumption
鈥?TTL and CMOS-Compatible Address and Enable Inputs
鈥?44V Maximum Power Supply Rating
鈥?High Latch-Up Immunity
鈥?Break-Before-Make Switching
鈥?Alternate Source
Applications
鈥?Data Acquisition Systems
鈥?Communication Systems
鈥?Signal Multiplexing/Demultiplexing
鈥?Audio Signal Multiplexing
Part Number Information
PART NUMBER
DG506AAK
DG506ACJ
DG506ACY
DG507ABK
TEMP.
RANGE (
o
C)
-55 to 125
0 to 70
0 to 70
-25 to 85
PACKAGE
28 Ld CERDIP
28 Ld PDIP
28 Ld SOIC
28 Ld CERDIP
PKG.
NO.
F28.6
E28.6
M28.3
F28.6
PART NUMBER
DG507ACJ
DG507ACY
DG509ACJ
DG509ACY
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
28 Ld PDIP
28 Ld SOIC
16 Ld PDIP
16 Ld SOIC
PKG.
NO.
E28.6
M28.3
E16.3
M16.3
Pinouts
DG506A (PDIP, CERDIP, SOIC)
TOP VIEW
V+ 1
NC 2
NC 3
S
16
4
S
15
5
S
14
6
S
13
7
S
12
8
S
11
9
S
10
10
S
9
11
GND 12
NC 13
A
3
14
28 D
27 V-
26 S
8
25 S
7
24 S
6
23 S
5
22 S
4
21 S
3
20 S
2
19 S
1
18 EN
17 A
0
16 A
1
15 A
2
DG507A (PDIP, CERDIP, SOIC)
TOP VIEW
V+ 1
D
B
2
NC 3
S
8B
4
S
7B
5
S
6B
6
S
5B
7
S
4B
8
S
3B
9
S
2B
10
S
1B
11
GND 12
NC 13
NC 14
28 D
A
27 V-
26 S
8A
25 S
7A
24 S
6A
23 S
5A
22 S
4A
21 S
3A
20 S
2A
19 S
1A
18 EN
17 A
0
16 A
1
15 A
2
DG509A (PDIP, SOIC)
TOP VIEW
A
0
1
EN 2
V- 3
S
1A
S
2A
S
3A
S
4A
4
5
6
7
16 A
1
15 GND
14 V+
13 S
1B
12 S
2B
11 S
3B
10 S
4B
9 D
B
D
A
8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
|
Copyright 漏 Intersil Americas Inc. 2001

DG507ABK 產(chǎn)品屬性

  • Maxim Integrated Products

  • 1 Channel

  • 450 Ohms

  • 600 ns

  • 1000 ns

  • 400 ns

  • - 0.07 mA at - 15 V, 0.13 mA at 15 V

  • 1200 mW

  • + 85 C

  • - 25 C

  • CDIP W

  • Through Hole

  • 1200 mW

  • 0.13 mA

  • Analog Multiplexer

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