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Five equally spaced outputs
Fits standard 8-pin DIP socket
Low profile
Auto-insertable
Input & outputs fully TTL interfaced & buffered
10 T
2
L fan-out capability
IN
T2
T4
GND
1
2
3
4
8
7
6
5
data
3
廬
delay
devices,
inc.
PACKAGES
VCC
T1
T3
T5
IN
N/C
N/C
T2
N/C
T4
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
N/C
T1
N/C
T3
N/C
T5
DDU8F-xx
DDU8F-xxA1
DDU8F-xxB1
DDU8F-xxM
DIP
Gull-Wing
J-Lead
Military DIP
Military SMD
DDU8F-xxMD1
DDU8F-xxMD4
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The DDU8F-series device is a 5-tap digitally buffered delay line. The
IN
Signal Input
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
T1-T5 Tap Outputs
amount determined by the device dash number (See Table). For dash
VCC +5 Volts
numbers less than 5025, the total delay of the line is measured from T1 to
GND Ground
T5. The nominal tap-to-tap delay increment is given by one-fourth of the
total delay, and the inherent delay from IN to T1 is nominally 3.5ns. For dash numbers greater than or
equal to 5025, the total delay of the line is measured from IN to T5. The nominal tap-to-tap delay
increment is given by one-fifth of this number.
SERIES SPECIFICATIONS
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Minimum input pulse width:
40% of total delay
Output rise time:
2ns typical
Supply voltage:
5VDC
鹵
5%
Supply current:
I
CCL
= 32ma typical
I
CCH
= 7ma typical
Operating temperature:
0擄 to 70擄 C
Temp. coefficient of total delay:
100 PPM/擄C
DASH NUMBER SPECIFICATIONS
Part
Number
DDU8F-5004
DDU8F-5006
DDU8F-5008
DDU8F-5010
DDU8F-5012
DDU8F-5016
DDU8F-5020
DDU8F-5025
DDU8F-5030
DDU8F-5035
DDU8F-5040
DDU8F-5045
DDU8F-5050
DDU8F-5060
DDU8F-5075
DDU8F-5100
DDU8F-5125
DDU8F-5150
DDU8F-5175
DDU8F-5200
DDU8F-5250
Total
Delay (ns)
4
鹵
1.0 *
6
鹵
1.0 *
8
鹵
2.0 *
10
鹵
2.0 *
12
鹵
2.0 *
16
鹵
2.0 *
20
鹵
3.0 *
25
鹵
3.0
30
鹵
3.0
35
鹵
3.0
40
鹵
3.0
45
鹵
3.0
50
鹵
3.0
60
鹵
3.0
75
鹵
4.0
100
鹵
5.0
125
鹵
6.5
150
鹵
7.5
175
鹵
8.0
200
鹵
10.0
250
鹵
12.5
Delay Per
Tap (ns)
1.0
鹵
0.5
1.5
鹵
0.5
2.0
鹵
1.0
2.5
鹵
1.0
3.0
鹵
1.0
4.0
鹵
1.5
5.0
鹵
2.0
5.0
鹵
2.0
6.0
鹵
2.0
7.0
鹵
2.0
8.0
鹵
2.0
9.0
鹵
3.0
10.0
鹵
3.0
12.0
鹵
3.0
15.0
鹵
3.0
20.0
鹵
3.0
25.0
鹵
3.0
30.0
鹵
3.0
35.0
鹵
4.0
40.0
鹵
4.0
50.0
鹵
5.0
3.5ns
25%
25%
25%
25%
VCC IN
T1
T2
T3
T4
T5 GND
Functional diagram for dash numbers < 5025
20%
20%
20%
20%
20%
VCC IN
T1
T2
T3
T4
T5 GND
* Total delay is referenced to first tap output
Input to first tap = 3.5ns
鹵
1ns
NOTE: Any dash number between 5004 and 5250
not shown is also available.
Functional diagram for dash numbers >= 5025
漏
1997 Data Delay Devices
Doc #97012
1/28/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
DDU8F-5035相關(guān)型號PDF文件下載
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, TTL-INTERFACED FIXED DELAY LINE
ETC
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英文版
5-TAP, TTL-INTERFACED
FIXED DELAY LINE
DATA DELAY DEVI...
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英文版
5-TAP, TTL-INTERFACED FIXED DELAY LINE
-
英文版
5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE
ETC
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英文版
5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, TTL-INTERFACED FIXED DELAY LINE
ETC
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