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Five equally spaced outputs
Fits standard 8-pin DIP socket
Low profile
Auto-insertable
Input & outputs fully CMOS interfaced & buffered
2
10 T L fan-out capability
IN
T2
T4
GND
data
3
廬
delay
devices,
inc.
PACKAGES
1
2
3
4
8
7
6
5
VDD
T1
T3
T5
DDU8C3-xx
DIP
DDU8C3-xxA1 Gull-Wing
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The DDU8C3-series device is a 5-tap digitally buffered delay line. The
IN
Signal Input
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
T1-T5 Tap Outputs
amount determined by the device dash number (See Table). For dash
VDD
+3.3 Volts
numbers 5020 and above, the total delay of the line is measured from IN to
GND Ground
T5, and the nominal tap-to-tap delay increment is given by one-fifth of the
total delay. For dash numbers below 5020, the total delay is measured from T1 to T5, and the delay
increment is given by one-fourth of the total delay.
SERIES SPECIFICATIONS
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Minimum input pulse width:
40% of total delay
Output rise time:
2ns typical
Supply voltage:
3.3VDC
鹵
0.3V
Supply current:
I
CCL
= 40碌a typical
I
CCH
= 7ma typical
Operating temperature:
-40擄 to 85擄 C
Temp. coefficient of total delay:
300 PPM/擄C
DASH NUMBER SPECIFICATIONS
Part
Number
DDU8C3-5004
DDU8C3-5006
DDU8C3-5008
DDU8C3-5010
DDU8C3-5012
DDU8C3-5014
DDU8C3-5020
DDU8C3-5025
DDU8C3-5030
DDU8C3-5035
DDU8C3-5040
DDU8C3-5045
DDU8C3-5050
DDU8C3-5060
DDU8C3-5075
DDU8C3-5100
DDU8C3-5125
DDU8C3-5150
DDU8C3-5175
DDU8C3-5200
DDU8C3-5250
Total
Delay (ns)
4
鹵
1.0 *
6
鹵
1.0 *
8
鹵
2.0 *
10
鹵
2.0 *
12
鹵
2.0 *
14
鹵
2.0 *
20
鹵
2.0
25
鹵
2.0
30
鹵
2.0
35
鹵
2.0
40
鹵
2.0
45
鹵
2.25
50
鹵
2.5
60
鹵
3.0
75
鹵
3.75
100
鹵
5.0
125
鹵
6.5
150
鹵
7.5
175
鹵
8.0
200
鹵
10.0
250
鹵
12.5
Delay Per
Tap (ns)
1.0
鹵
0.5
1.5
鹵
0.5
2.0
鹵
1.0
2.5
鹵
1.0
3.0
鹵
1.0
3.5
鹵
1.0
4.0
鹵
1.0
5.0
鹵
1.5
6.0
鹵
1.5
7.0
鹵
1.8
8.0
鹵
2.0
9.0
鹵
2.0
10.0
鹵
2.0
12.0
鹵
2.0
15.0
鹵
2.5
20.0
鹵
3.0
25.0
鹵
3.0
30.0
鹵
3.0
35.0
鹵
4.0
40.0
鹵
4.0
50.0
鹵
5.0
3.0ns
25%
25%
25%
25%
VDD IN
T1
T2
T3
T4
T5 GND
Functional diagram for dash numbers < 5020
20%
20%
20%
20%
20%
VDD IN
T1
T2
T3
T4
T5 GND
Functional diagram for dash numbers >= 5020
* Total delay is referenced to first tap output
Input to first tap = 3.0ns
鹵
1ns
NOTE: Any dash number between 5004 and 5250
not shown is also available.
漏
2000 Data Delay Devices
Doc #00115
5/19/00
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
DDU8C3-5060相關(guān)型號PDF文件下載
-
型號
版本
描述
廠商
下載
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
-
英文版
5-TAP, TTL-INTERFACED FIXED DELAY LINE
ETC
-
英文版
5-TAP, TTL-INTERFACED
FIXED DELAY LINE
DATA DELAY DEVI...
-
英文版
5-TAP, TTL-INTERFACED FIXED DELAY LINE
-
英文版
5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE
ETC
-
英文版
5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE
-
英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
-
英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
-
英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
-
英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
DATADELAY ...
-
英文版
5-TAP, TTL-INTERFACED FIXED DELAY LINE
ETC
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