鈥?/div>
Ten equally spaced outputs
Fits standard 16-pin DIP socket
Low profile
Auto-insertable
Input & outputs fully CMOS interfaced & buffered
10 T
2
L fan-out capability
IN
T2
T4
T6
T8
T10
N/C
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
T1
T3
T5
T7
T9
data
3
廬
delay
devices,
inc.
PACKAGES
VDD
IN
N/C
T2
T4
T6
T8
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
T1
T3
T5
T7
T9
T10
N/C
N/C
DDU7C-xx
DDU7C-xxA3
DDU7C-xxB3
DDU7F-xxMC3
DIP
Gull-Wing
J-Lead
Military SMD
Military DIP
DDU7C-xxM
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The DDU7C-series device is a 10-tap digitally buffered delay line. The
IN
Signal Input
signal input (IN) is reproduced at the outputs (T1-T10), shifted in time by an
T1-T10 Tap Outputs
amount determined by the device dash number. The nominal tap-to-tap
VDD +5 Volts
delay increment is given by 1/10 of the dash number. For dash numbers
GND Ground
less than 50, the total delay of the line is measured from T1 to T10, with the
nominal value given by 9 times the increment. The inherent delay from IN to T1 is nominally 8.0ns. For
dash numbers greater than or equal to 50, the total delay of the line is measured from IN to T10, with the
nominal value given by the dash number.
SERIES SPECIFICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Minimum input pulse width:
20% of total delay
Output rise time:
8ns typical
Supply voltage:
5VDC
鹵
5%
Supply current:
I
CCL
= 40碌a typical
I
CCH
= 10ma typical
Operating temperature:
0擄 to 70擄 C
Temp. coefficient of total delay:
300 PPM/擄C
3.5ns
10%
10%
10%
10%
10%
10%
10%
10%
10%
DASH NUMBER SPEC.鈥橲
Part
Number
DDU7C-25
DDU7C-100
DDU7C-150
DDU7C-200
DDU7C-250
DDU7C-300
DDU7C-400
DDU7C-500
Total
Delay (ns)
22.5
鹵
2.0 *
100
鹵
5.0
150
鹵
7.5
200
鹵
10.0
250
鹵
12.5
300
鹵
15.0
400
鹵
20.0
500
鹵
25.0
Delay Per
Tap (ns)
2.5
鹵
1.0
10.0
鹵
2.0
15.0
鹵
2.0
20.0
鹵
2.0
25.0
鹵
2.0
30.0
鹵
3.0
40.0
鹵
4.0
50.0
鹵
5.0
* Total delay is referenced to first tap
Input to first tap = 8.0ns
鹵
2ns
NOTE: Any dash number between 25 and
500 not shown is also available.
VCC IN
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 GND
Functional diagram for dash numbers < 50
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
VCC IN
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 GND
Functional diagram for dash numbers >= 50
漏
1997 Data Delay Devices
Doc #97019
1/30/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
DDU7C-500M相關(guān)型號(hào)PDF文件下載
-
型號(hào)
版本
描述
廠商
下載
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英文版
10-TAP, TTL-INTERFACED FIXED DELAY LINE
ETC
-
英文版
10-TAP, TTL-INTERFACED
FIXED DELAY LINE
DATA DELAY DEVI...
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英文版
10-TAP, TTL-INTERFACED FIXED DELAY LINE
-
英文版
10-TAP, TTL-INTERFACED FIXED DELAY LINE (SERIES DDU7F)
DATADELAY ...
-
英文版
DATA DELAY DEVI...
-
英文版
DIGITAL DELAY UNITS
DATADELAY ...
-
英文版
10 Taps (14 pins DIP) T2L Interfaced
ETC
-
英文版
10 Taps (14 pins DIP) T2L Interfaced
ETC [ETC]
-
英文版
10-TAP, TTL-INTERFACED FIXED DELAY LINE
ETC
-
英文版
10-TAP, TTL-INTERFACED FIXED DELAY LINE
-
英文版
Tapped Delay Line
-
英文版
Tapped Delay Line
-
英文版
Tapped Delay Line
-
英文版
Tapped Delay Line
-
英文版
10 Taps (14 pins DIP) T2L Interfaced
ETC
-
英文版
10 Taps (14 pins DIP) T2L Interfaced
ETC [ETC]
-
英文版
10-TAP, TTL-INTERFACED FIXED DELAY LINE
ETC
-
英文版
10-TAP, TTL-INTERFACED FIXED DELAY LINE
-
英文版
10-TAP, TTL-INTERFACED FIXED DELAY LINE
ETC
-
英文版
10-TAP, TTL-INTERFACED FIXED DELAY LINE
1
2
3
4
