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Five equally spaced outputs
Fits standard 8-pin DIP socket
Low profile
Auto-insertable
Input & outputs fully CMOS interfaced & buffered
2
10 T L fan-out capability
IN
1
14
12
T2
T4
GND
4
10
6
7
8
data
3
廬
delay
devices,
inc.
PACKAGES
VCC
T1
T3
T5
IN
N/C
N/C
T2
N/C
T4
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
N/C
T1
N/C
T3
N/C
T5
DIP
DDU4C-xx Comm.
DDU4C-xxM Military
SMD
DDU4C-xxA2 Comm.
DDU4C-xxB2 Comm.
DDU4C-xxMC2 Military
FUNCTIONAL DESCRIPTION
The DDU4C-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). The total
delay of the line is measured from IN to T5. The nominal tap-to-tap delay
increment is given by one-fifth of the total delay.
PIN DESCRIPTIONS
IN
T1-T5
VDD
GND
Signal Input
Tap Outputs
+5 Volts
Ground
SERIES SPECIFICATIONS
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鈥?/div>
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Minimum input pulse width:
20% of total delay
Output rise time:
8ns typical
Supply voltage:
5VDC
鹵
5%
Supply current:
I
CCL
= 40碌a typical
I
CCH
= 10ma typical
Operating temperature:
0擄 to 70擄 C
Temp. coefficient of total delay:
300 PPM/擄C
DASH NUMBER SPECIFICATIONS
Part
Number
DDU4C-5050
DDU4C-5060
DDU4C-5075
DDU4C-5100
DDU4C-5125
DDU4C-5150
DDU4C-5200
DDU4C-5250
DDU4C-5300
DDU4C-5400
DDU4C-5500
Total
Delay (ns)
50
鹵
2.5
60
鹵
3.0
75
鹵
4.0
100
鹵
5.0
125
鹵
6.5
150
鹵
7.5
200
鹵
10.0
250
鹵
12.5
300
鹵
15.0
400
鹵
20.0
500
鹵
25.0
Delay Per
Tap (ns)
10.0
鹵
3.0
12.0
鹵
3.0
15.0
鹵
3.0
20.0
鹵
3.0
25.0
鹵
3.0
30.0
鹵
3.0
40.0
鹵
4.0
50.0
鹵
5.0
60.0
鹵
6.0
80.0
鹵
8.0
100.0
鹵
10.0
NOTE: Any dash number between 5050 and 5500
not shown is also available.
20%
20%
20%
20%
20%
VDD IN
T1
T2
T3
T4
T5 GND
DDU4C Functional diagram
漏
1997 Data Delay Devices
Doc #97034
12/10/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
DDU4C-5500M相關(guān)型號PDF文件下載
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型號
版本
描述
廠商
下載
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英文版
DATA DELAY DEVI...
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
ETC
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4...
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英文版
5-TAP, TTL-INTERFACED FIXED DELAY LINE (SERIES DDU4F)
DATADELAY ...
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英文版
MECHANICALLY VARIABLE TTL DELAY LINE (SERIES DDU47F)
DATADELAY ...
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英文版
MECHANICALLY VARIABLE TTL DELAY LINE (SERIES DDU47F)
DATADELAY ...
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英文版
Logic IC
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
ETC
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英文版
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4...
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
ETC
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4...
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
ETC
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4...
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
ETC
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4...
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
ETC
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4...
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
ETC
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4...
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
ETC
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