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CYW2338 Datasheet

  • CYW2338

  • Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers

  • 12頁

  • CYPRESS

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12338\CYW2338
PRELIMINARY
CYW2338
Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers
Features
鈥?Operating voltage 2.7V to 5.5V
鈥?Operating frequency to 2.5 GHz on PLL1 and 1.1 GHz
on PLL2 with prescaler ratios of 64/65 and 128/129
鈥?Lock detect feature
鈥?Power-down mode I
CC
< 1 碌A(chǔ) typical at 3.0V
鈥?Serial data input accepts data clock rates as low as
1 kHz
鈥?Low power/voltage operation with low current standby
mode
鈥?On-chip reference oscillator
鈥?Available in a 20-pin TSSOP (Thin Shrink Small Outline
Package)
鈥?Available in a 24-pin CSP (Chip Scale Package)
鈥?Available in a 20-pin MLF
(Mirco Lead Frame Package)
Applications
The Cypress CYW2338 is a dual serial input PLL frequency
synthesizer designed for high performance dual conversion
TV, VCR, and Set-top tuner sections, as well as downstream
receivers for cable modems. The CYW2338 is also well suited
for high-volume, low-cost wireless communications applica-
tions. One 2.5-GHz and 1.1-GHz prescaler, each with pulse
swallow capability are included. The device operates from
2.7V and dissipates only 27 mW.
Dual PLL Block Diagram
F
IN
1 (5)
F
IN
1# (6)
Prescaler
64/65 or
128/129
GND (4)
GND (7)
V
CC
1 (1)
V
CC
2 (20)
V
P
1 (2)
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
fp1
Phase
Detector
Charge
Pump
D
O
PLL1 (3)
19-Bit
Latch
OSC_IN (8)
OSC_OUT (9)
Latch
Selector
LE (13)
DATA (12)
CLOCK (11)
Pwr-dwn
PLL1
fr1
fr fp
Monitor
Output
Selector
15-Bit
Reference Counter
20-Bit Latch
20-Bit Latch
15-Bit
Reference Counter
19-Bit
Latch
Pwr-dwn
PLL2
F
O
/LD (10)
fr2
Cntrl 22-Bit
Shift
Reg.
Power
Control
F
IN
2 (16)
F
IN
2# (15)
Prescaler
64/65 or
128/129
Binary 4-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
Phase
Detector
fp2
Charge
Pump
D
O
PLL2 (18)
GND (14)
Vcc1
Vcc2
GND (17)
V
P
2 (19)
Pin Configuration
V
CC
1
V
P
1
D
O
PLL1
GND
F
IN
1
F
IN
1#
GND
OSC_IN
OSC_OUT
F
O
/LD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
2
V
P
2
D
O
PLL2
GND
F
IN
2
F
IN
2#
GND
LE
DATA
CLOCK
NC
Vp1
DoPLL1
GND
Fin1
Fin1#
GND
OSC_IN
NC
1
2
3
4
5
6
7
8
Vp2
Vp1
20
19
18
DoPLL2
20
19
18
17
Vp2
24
23
22
21
NC
GND
Fin2
Fin2#
GND
LE
DATA
NC
DoPLL1
GND
Fin1
Fin1#
GND
16
DoPLL2
Vcc1
Vcc2
1
2
3
4
5
10
6
15
14
GND
Fin2
Fin2#
GND
LE
(Top View)
17
16
15
14
(Top View)
13
12
11
10
11
12
7
8
9
13
OSC_OUT
GND
Fo/LD
CLOCK
Fo/LD
9
OSC_OUT
GND
TSSOP
CSP
OSC_IN
MLF
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
February 6, 2001, rev. **
CLOCK
DATA

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