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CYV15G0401DXB-BGI Datasheet

  • CYV15G0401DXB-BGI

  • Quad HOTLink II Transceiver

  • 53頁

  • CYPRESS

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CYP15G0401DXB
CYV15G0401DXB
Quad HOTLink II鈩?Transceiver
Features
鈥?Quad channel transceiver for 195 to 1500 MBaud serial
signaling rate
鈥?Aggregate throughput of 12 GBits/second
鈥?Second-generation HOTLink
廬
technology
鈥?Compliant to multiple standards
鈥?ESCON, DVB-ASI, Fibre Channel and Gigabit
Ethernet (IEEE802.3z)
鈥?CYV15G0401DXB also compliant to SMPTE 259M
and SMPTE 292M
鈥?8B/10B encoded or 10-bit unencoded data
鈥?Selectable parity check/generate
鈥?Selectable multi-channel bonding options
鈥?Four 8-bit channels
鈥?Two 16-bit channels
鈥?One 32-bit channel
鈥?N x 32-bit channel support (inter-chip)
鈥?Skew alignment support for multiple bytes of offset
鈥?Selectable input/output clocking options
鈥?MultiFrame鈩?Receive Framer
鈥?Bit and Byte alignment
鈥?Comma or full K28.5 detect
鈥?Single- or multi-byte framer for byte alignment
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Low-latency option
Synchronous LVTTL parallel interface
Optional Elasticity Buffer in Receive Path
Optional Phase Align Buffer in Transmit Path
Internal phase-locked loops (PLLs) with no external
PLL components
10
10
鈥?Dual differential PECL-compatible serial inputs per
channel
鈥?Internal DC-restoration
鈥?Dual differential PECL-compatible serial outputs per
channel
鈥?/div>
Source matched for 50鈩?transmission lines
鈥?No external bias resistors required
鈥?Signaling-rate controlled edge-rates
鈥?Compatible with
鈥?fiber-optic modules
鈥?copper cables
鈥?circuit board traces
鈥?JTAG boundary scan
鈥?Built-In Self-Test (BIST) for at-speed link testing
鈥?Per-channel Link Quality Indicator
鈥?Analog signal detect
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Digital signal detect
Low power 2.5W @ 3.3V typical
Single 3.3V supply
256-ball thermally enhanced BGA
0.25碌 BiCMOS technology
Functional Description
The CYP(V)15G0401DXB
[1]
Quad HOTLink II鈩?Transceiver
is a point-to-point or point-to-multipoint communications
building block allowing the transfer of data over high-speed
serial links (optical fiber, balanced, and unbalanced copper
transmission lines) at signaling speeds ranging from
195-to-1500 MBaud per serial link.
10
Serial Links
10
CYP15G0401DXB
System Host
10
10
10
10
10
Serial Links
10
10
10
10
Serial Links
Backplane or
Cabled
Connections
Note:
1. CYV15G0401DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0401DXB refers to devices not compliant to SMPTE 259M and SMPTE
292M pathological test requirements. CYP(V)15G0401DXB refers to both devices.
Figure 1. HOTLink II System Connections
Cypress Semiconductor Corporation
Document #: 38-02002 Rev. *K
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised March 16, 2004
System Host
Serial Links
CYP15G0401DXB
10
10
10

CYV15G0401DXB-BGI 產(chǎn)品屬性

  • 40

  • 集成電路 (IC)

  • 接口 - 驅(qū)動器，接收器，收發(fā)器

  • HOTlink II™

  • 收發(fā)器

  • 4/4

  • 多協(xié)議

  • 3.135 V ~ 3.465 V

  • 表面貼裝

  • 256-LBGA 裸露焊盤

  • 256-BGA

  • 托盤

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