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CYP15G0402DX-BGI Datasheet

  • CYP15G0402DX-BGI

  • Quad HOTLinkII SERDES

  • 27頁

  • CYPRESS

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PRELIMINARY
CYP15G0402DX
Quad HOTLinkII鈩?SERDES
Features
鈥?Second generation HOTLink
廬
technology
鈥?Fibre-Channel and Gigabit-Ethernet-compliant
鈥?10-bit unencoded data transport
鈥?Aggregate throughput of 12 GB/s
鈥?Selectable parity check/generate
鈥?Four independently controlled 10-bit channels
鈥?Selectable input clocking options
鈥?User selectable framing character
鈥?+Comma, 鹵comma, or full K28.5 detect
鈥?Single or multicharacter framer for character align-
ment
鈥?Low-latency option
鈥?Synchronous parallel input interface
鈥?User-configurable threshold level
鈥?Compatible with LVTTL, LVCMOS, LVTTL
鈥?Synchronous parallel output interface
鈥?Compatible with LVTTL, LVCMOS, LVTTL
鈥?200-to-1500 MBaud serial signaling rate
鈥?Internal PLLs with no external PLL components
鈥?Separate clock and data-recovery PLL per channel
鈥?Common transmit clock multiplier PLL
鈥?Differential PECL-compatible serial inputs
鈥?Differential PECL-compatible serial outputs
鈥?/div>
Source matched for 50鈩?transmission lines
鈥?No external resistors required
鈥?/div>
Adjustable amplitude for 100鈩?or 150鈩?balanced
loads
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Compatible with fiber-optic modules and copper cables
JTAG boundary scan
Built-in self-test (BIST) for at-speed link testing
Per-channel Link Quality Indicator
鈥?Analog signal detect
鈥?Digital signal detect
鈥?Low-power 3W typical
鈥?256-ball BGA
鈥?/div>
0.25碌 BiCMOS technology
Functional Description
The CYP15G0402DX Quad HOTLinkII鈩?SERDES is a
point-to-point communications building block allowing the
transfer of pre-encoded data over high-speed serial links
(optical fiber, balanced, and unbalanced copper transmission
lines) at speeds ranging from 200 to 1500 MBaud per serial
link.
Each transmit channel accepts pre-encoded 10-bit trans-
mission characters in an input register, serializes each
character, and drives it out a PECL-compatible differential line
driver. Each receive channel accepts a serial data stream at a
differential line receiver, deserializes the stream into 10-bit
characters, frames these characters to the proper 10-bit
character boundaries, and this data becomes register outputs
with a recovered character clock.
Figure 1
illustrates typical
connections between independent systems and a
CYP15G0402DX.
As
a
second-generation
HOTLink
device,
the
CYP15G0402DX extends the HOTLink family to faster data
rates, while maintaining serial link compatibility with other
HOTLink devices.
10
Serial Links
10
Independent
Channel
Transceiver
Independent
Channel
Transceiver
Independent
Channel
Transceiver
Independent
Channel
Transceiver
10
10
System Host With Encoder/Decoder
Cypress Semiconductor Corporation
Document #: 38-02023 Rev. *B
System Host With Encoder/Decoder
10
10
CYP15G0402DX
10
10
Serial Links
10
10
10
10
Serial Links
10
10
10
10
Serial Links
Cable or
Optical
Connections
Figure 1. CYP15G0402DX HOTLink II鈩?System Connections
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised February 14, 2002

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