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CYP15G0401DXA-BGI Datasheet

  • CYP15G0401DXA-BGI

  • Quad HOTLink II Transceiver

  • 1052.62KB

  • 48頁

  • CYPRESS

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PRELIMINARY
CYP15G0401DXA
Quad HOTLink II鈩?Transceiver
Features
鈥?2
nd
generation HOTLink廬 technology
鈥?Fibre Channel and Gigabit Ethernet compliant 8B/10B-
coded or 10-bit unencoded
鈥?8-bit encoded data transport
鈥?10-bit unencoded data transport
鈥?Selectable parity check/generate
鈥?Selectable multi-channel bonding options
鈥?Four 8-bit channels
鈥?Two 16-bit channels
鈥?One 32-bit channel
鈥?N x 32-bit channel support (inter-chip)
鈥?Selectable input clocking options
鈥?Selectable output clocking options
鈥?MultiFrame鈩?receive framer provides alignment to
鈥?Bit, byte, half-word, word, multi-word
鈥?COMMA or Full K28.5 detect
鈥?Single or Multi-byte framer for byte alignment
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Low-latency option
Skew alignment support for multiple bytes of offset
Synchronous LVTTL parallel input interface
Synchronous LVTTL parallel output interface
200-to-1500 MBaud serial signaling rate
Internal PLLs with
no
external PLL components
Dual differential PECL-compatible serial inputs per
channel
Dual differential PECL-compatible serial outputs per
channel
鈥?Source matched for 50鈩?transmission lines
鈥?No external bias resistors required
鈥?Signaling-rate controlled edge-rates
鈥?Compatible with
鈥?fiber-optic modules
鈥?copper cables
鈥?circuit board traces
鈥?JTAG boundary scan
鈥?Built-In Self-Test (BIST) for at-speed link testing
鈥?Per-channel Link Quality Indicator
鈥?Analog signal detect
鈥?Digital signal detect
鈥?Frequency range detect
鈥?Low Power (2.8W typical)
鈥?Single +3.3V V
CC
supply
鈥?256-ball Thermally Enhanced BGA
鈥?/div>
0.25碌 BiCMOS technology
Functional Description
The CYP15G0401DXA Quad HOTLink II鈩?Transceiver is a
point-to-point or point-to-multipoint communications building
block allowing the transfer of data over high-speed serial links
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 200-to-1500 MBaud
per serial link. The multiple channels in each device may be
combined to allow transport of wide buses across significant
distances with minimal concern for offsets in clock phase or
link delay.
Each transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and converts
it to serial data. Each receive channel accepts serial data and
converts it to parallel data, decodes the data into characters,
and presents these characters to an output register.
Figure 1
illustrates typical connections between independent host sys-
tems and corresponding CYP15G0401DXA parts. As a sec-
ond-generation HOTLink device, the CYP15G0401DXA ex-
tends the HOTLink family with enhanced levels of integration
and faster data rates, while maintaining serial-link compatibility
(data, command, and BIST) with other HOTLink devices.
10
10
Serial Links
10
10
CYP15G0401DXA
CYP15G0401DXA
10
System Host
10
10
10
Serial Links
Cypress Semiconductor Corporation
Document #: 38-02002 Rev. *B
System Host
10
10
10
10
Serial Links
10
10
10
Serial Links
Backplane or
Cabled
Connections
10
Figure 1. HOTLink II鈩?System Connections
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised July 10, 2001

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