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CYM9261B-66C Datasheet

  • CYM9261B-66C

  • 64K(128K, 256K, 512K) x 72 SRAM Module

  • 12頁

  • CYPRESS

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62A
CYM9260
CYM9261B
CYM9262A
CYM9263
64K x 72 SRAM Module
128K x 72 SRAM Module
256K x 72 SRAM Module
512K x 72 SRAM Module
Features
鈥?Operates at 66 MHz
鈥?Uses 64K x 18, 128K x 18, or 256K x 18 high performance
synchronous SRAMs
鈥?168-position Angled DIMM from Amp p/n 179508-2
鈥?3.3V inputs/data outputs
surface mount packages on an epoxy laminate board with
pins. The modules are designed to be incorporated into large
memory arrays.
The module is configured as either one or two banks, where
each bank has separate chip select and output enable con-
trols. Separate clocks are provided for every pair of SRAMs鈥檚.
Multiple ground pins and on-board decoupling capacitors en-
sure high performance with maximum noise immunity.
All components on the cache modules are surface mounted on
a multi-layer epoxy laminate (FR-4) substrate. The contact
pins are plated with 150 micro-inches of nickel covered by 30
micro-inches of gold flash.
Functional Description
The CYM9260, CYM9261, CYM9262, and the CYM9263 are
high-performance synchronous memory modules organized
as 64K(9260), 128K(9261), 256K(9262), or 512K(9263) by 72
bits. These modules are constructed from either 128K x
18(9260,9261B,9262A) or 256K x 18 (9263) SRAMs in plastic
Logic Block Diagram- CYM9260
V
cc3
A[15:0]
WE[7:0]
ADSP
OE[0:1]
OE0
CS[0:1]
CS0
R3
A
15:0
ADSP
OE
CS
WEH
R1
WEL
ADSC
BANK 0
CLK[0:3]
CLK
CLK[0]
CLK[1]
CLK[2]
CLK[3]
V
cc3
R2
DQ[0:15]
DQP[0:1]
(4) 64K x 18 SRAM
R4
D[0:63]
DP[0:7]
R1, R2, R3, R4 are optional resistors
R1, R2, R4 are mounted for access using ADSC
R3, R2, R4 are mounted for access using ADSP
64Kx72
PD
1
GND
PD
0
NC
BANK 0
Cypress Semiconductor Corporation
Document #: 38-05002 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised March 27, 2002

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