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CYM1851P6-20C Datasheet

  • CYM1851P6-20C

  • 1,024K x 32 Static RAM Module

  • 9頁(yè)

  • CYPRESS

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51
CYM1851
1,024K x 32 Static RAM Module
Features
鈥?High-density 32-megabit SRAM module
鈥?32-bit Standard Footprint supports densities from 16K
x 32 through 1M x 32
鈥?High-speed SRAMs
鈥?Access time of 12 ns
鈥?Low active power
鈥?8.36W (max.) at 12 ns
鈥?72 pins
鈥?Available in ZIP, SIMM, or angled SIMM format
mounted on an epoxy laminate substrate. Four chip selects are
used to independently enable the four bytes. Reading or writ-
ing can be executed on individual bytes or any combination of
multiple bytes through proper use of selects.
The CYM1851 is designed for use with standard 72-pin SIMM
sockets. The pinout is downward compatible with the 64-pin
JEDEC ZIP/SIMM module family (CYM1821, CYM1831,
CYM1836, and CYM1841). Thus, a single motherboard de-
sign can be used to accommodate memory depth ranging from
16K words (CYM1821) to 1,024K words (CYM1851). The
CYM1851 is offered in vertical and angled SIMM configura-
tions and both are available with either tin-lead or 10 mi-
cro-inches of gold flash on the edge contacts.
Presence detect pins (PD
0
鈥揚(yáng)D
3
) are used to identify module
memory density in applications where modules with alternate
word depths can be interchanged.
Functional Description
The CYM1851 is a high-performance 32-megabit static RAM
module organized as 1,024K words by 32 bits. This module is
constructed from eight 1,024K x 4 SRAMs in SOJ packages
Logic Block Diagram
PD
0
-
PD
1
-
PD
2
-
PD
3
-
GND
OPEN
GND
OPEN
Pin Configuration
ZIP/SIMM
Top View
A
0
鈥揂
19
OE
WE
20
1M x 4
SRAM
CS
1
1M x 4
SRAM
CS
2
1M x 4
SRAM
CS
3
1M x 4
SRAM
CS
4
4
I/O
0
鈥?I/O
3
1M x 4
SRAM
4
I/O
4
鈥?I/O
7
4
I/O
8
鈥?I/O
11
1M x 4
SRAM
4
I/O
12
鈥?I/O
15
4
I/O
16
鈥?I/O
19
1M x 4
SRAM
NC
PD
3
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
14
CS
1
CS
3
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
A
19
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NC
PD
2
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
A
17
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
A
18
NC
4
I/O
20
鈥?I/O
23
4
I/O
24
鈥?I/O
27
1M x 4
SRAM
4
I/O
28
鈥?I/O
31
Cypress Semiconductor Corporation
Document #: 38-05274 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised March 15, 2002

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