41
CYM1441
256K x 8 Static RAM Module
Features
鈥?High-density 2-megabit SRAM module
鈥?High-speed CMOS SRAMs
鈥?Access time of 20 ns
鈥?Low active power
鈥?5.3W (max.)
鈥?SMD technology
鈥?Separate data I/O
鈥?60-pin ZIP package
鈥?TTL-compatible inputs and outputs
鈥?Low profile
鈥?Max. height of 0.5 in.
鈥?Small PCB footprint
鈥?1.14 sq. in.
Functional Description
The CYM1441 is a very high performance 2-megabit static
RAM module organized as 256K words by 8 bits. The module
is constructed using eight 256K x 1 static RAMs in SOJ pack-
ages mounted onto an epoxy laminate substrate with pins. Two
chip selects (CS
L
and CS
U
) are used to independently enable
the upper and lower 4 bits of the data word. Writing to the
memory module is accomplished when the chip select (CS)
and write enable (WE) inputs are both LOW. Data on the eight
input pins (DI
0
through DI
7
) is written into the memory location
specified on the address pins (A
0
through A
17
). Reading the
device is accomplished by taking chip select (CS) LOW while
write enable (WE) remains inactive or HIGH. Under these con-
ditions, the contents of the memory location specified on the
address pins will appear on the appropriate data output pins
(DO
0
through DO
7
). The data output pins remain in a high-
impedance state unless the module is selected and write en-
able (WE) is HIGH.Two pins (PD
0
and PD
1
) are used to identify
module memory density in applications where alternate ver-
sions of the JEDEC-standard modules can be interchanged.
Logic Block Diagram
A
0
- A
17
WE
CS
U
Pin Configuration
ZIP
TopView
(OPEN)PD
0
NC
V
CC
DI
0
DO
0
A
0
A
2
A
4
256K x 1
A
6
SRAM
GND
DI
1
DO
1
WE
DO
4
- DO
7
A
9
CS
L
NC
NC
V
CC
DI
2
DO
2
A
10
A
12
A
14
A
16
NC
DI
3
DO
3
NC
NC
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
256K x 1
SRAM
256K x 1
SRAM
256K x 1
SRAM
DI
4
- DI
7
CS
L
GND
PD
1
(GND)
NC
DI
4
DO
4
NC
A
1
A
3
A
5
A
7
DI
5
DO
5
V
CC
A
8
NC
CS
U
NC
NC
DI
6
DO
6
GND
A
11
A
13
A
15
A
17
DI
7
DO
7
V
CC
NC
NC
256K x 1
SRAM
256K x 1
SRAM
256K x 1
SRAM
256K x 1
SRAM
DI
0
- DI
3
DO
0
- DO
3
Cypress Semiconductor Corporation
Document #: 38-05271 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised March 15, 2002
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