CYK128K16SCCB
2-Mbit (128K x 16) Pseudo Static RAM
Features
鈥?Advanced low-power MoBL
廬
architecture
鈥?High speed: 55 ns, 70 ns
鈥?Wide voltage range: 2.7V to 3.3V
鈥?Typical active current: 1 mA @ f = 1 MHz
鈥?Low standby power
鈥?Automatic power-down when deselected
Functional Description
[1]
The CYK128K16SCCB is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 128K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life鈩?(MoBL)
in portable applications such as cellular telephones. The
device can be put into standby mode, reducing power
consumption dramatically when deselected (CE
1
LOW, CE
2
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O
0
through I/O
15
) are placed in a high-impedance state
when the chip is deselected (CE
1
HIGH, CE
2
LOW) or OE is
deasserted HIGH), or during a write operation (Chip Enabled
and Write Enable WE LOW). Reading from the device is
accomplished by asserting the Chip Enables (CE
1
LOW and
CE
2
HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the Truth Table for a complete description of read and write
modes.
Logic Block Diagram
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
DATA IN DRIVERS
ROW DECODER
128K x 16
RAM Array
SENSE AMPS
I/O
0
鈥揑/O
7
I/O
8
鈥揑/O
15
COLUMN DECODER
BHE
WE
OE
BLE
BHE
BLE
CE
2
CE
1
CE
2
CE
1
A
11
A
12
A
13
A
14
A
15
Pow
-
er Down
Circuit
Note:
1. For best-practice recommendations, please refer to the Cypress application note 鈥淪ystem Design Guidelines鈥?on http://www.cypress.com.
A
16
Cypress Semiconductor Corporation
Document #: 38-05525 Rev. *F
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised January 26, 2005
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