CYK128K16MCCB
2-Mbit (128K x 16) Pseudo Static RAM
Features
鈥?Wide voltage range: 2.70V鈥?.30V
鈥?Access Time: 55 ns, 70 ns
鈥?Ultra-low active power
鈥?Typical active current: 1mA @ f = 1 MHz
鈥?Typical active current: 14 mA @ f = f
max
(For 55-ns)
鈥?Typical active current: 8 mA @ f = f
max
(For 70-ns)
鈥?Ultra low standby power
鈥?Automatic power-down when deselected
鈥?CMOS for optimum speed/power
鈥?Offered in a 48-ball BGA Package
can be put into standby mode when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O
0
through I/O
15
) are placed in a high-impedance state when the
chip is deselected (CE HIGH), or when the outputs are
disabled (OE HIGH), or when both Byte High Enable and Byte
Low Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW and WE LOW).
Writing to the device is accomplished by asserting Chip
Enable (CE LOW) and Write Enable (WE) input LOW. If Byte
Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
17
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written
into the location specified on the address pins (A
0
through
A
16
).
Reading from the device is accomplished by asserting Chip
Enable (CE LOW) and Output Enable (OE) LOW while forcing
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O
0
to I/O
7
. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O
8
to
I/O
15
. Refer to the truth table for a complete description of read
and write modes.
Functional
Description
[1]
The CYK128K16MCCB is a high-performance CMOS Pseudo
Static RAM organized as 128K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life鈩?(MoBL
廬
) in
portable applications such as cellular telephones. The device
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
128K 脳 16
RAM Array
SENSE AMPS
I/O0 鈥?I/O7
I/O8 鈥?I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Power- Down
Circuit
A
11
A
12
A
13
A
14
A
15
A
16
BHE
BLE
CE
Note:
1. For best practice recommendations, please refer to the Cypress application note 鈥淪ystem Design Guidelines鈥?on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05584 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised January 27, 2005
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