PRELIMINARY
CY9C62256
32K x 8 Magnetic Nonvolatile CMOS RAM
Features
鈥?100% form, fit, function-compatible with 32K 脳 8
micropower SRAM (CY62256)
鈥?Fast Read and Write access: 70 ns
鈥?Voltage range: 4.5V鈥?.5V operation
鈥?Low power: 330 mW Active; 495
碌W
standby
鈥?Easy memory expansion with CE and OE features
鈥?TTL-compatible inputs and outputs
鈥?Automatic power-down when deselected
鈥?Replaces 32K 脳 8 Battery Backed (BB)SRAM, SRAM,
EEPROM, FeRAM or Flash memory
鈥?Data is automatically Write protected during power loss
鈥?Write Cycles Endurance: > 10
15
cycles
鈥?Data Retention: > 10 Years
鈥?Shielded from external magnetic fields
鈥?Extra 64 Bytes for device identification and tracking
鈥?Temperature ranges
鈥?Commercial: 0擄C to 70擄C
鈥?Industrial: 鈥?40擄C to 85擄C
鈥?JEDEC STD 28-pin DIP (600-mil), 28-pin (300-mil) SOIC,
and 28-pin TSOP-1 packages. Also available in 450-mil
wide (300-mil body width) 28-pin narrow SOIC.
Functional Description
The CY9C62256 is a high-performance CMOS nonvolatile
RAM employing an advanced magnetic RAM (MRAM)
process. An MRAM is nonvolatile memory that operates as a
fast read and write RAM. It provides data retention for more
than ten years while eliminating the reliability concerns,
functional disadvantages and system design complexities of
battery-backed SRAM, EEPROM, Flash and FeRAM. Its fast
writes and high write cycle endurance makes it superior to
other types of nonvolatile memory.
The CY9C62256 operates very similarly to SRAM devices.
Memory read and write cycles require equal times. The MRAM
memory is nonvolatile due to its unique magnetic process.
Unlike BBSRAM, the CY9C62256 is truly a monolithic nonvol-
atile memory. It provides the same functional benefits of a fast
write without the serious disadvantages associated with
modules and batteries or hybrid memory solutions.
These capabilities make the CY9C62256 ideal for nonvolatile
memory applications requiring frequent or rapid writes in a
bytewide environment.
The CY9C62256 is offered in both commercial and industrial
temperature ranges.
Logic Block Diagram
Pin Configurations
SOIC/DIP
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
INPUTBUFFER
A
11
A
10
A
9
A
8
A
7
A
6
A
3
A
2
A
1
CE
WE
OE
A
5
A
4
A
14
A
13
A
12
A
0
ROW DECODER
I/O
0
I/O
1
SENSE AMPS
Silicon Sig.
512x512
Y
ARRA
I/O
2
I/O
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
21
20
19
18
17
16
15
14
13
12
11
10
9
8
I/O
4
I/O
5
COLUMN
DECODER
POWER
DOWN &
WRITE
PROTECT
I/O
6
I/O
7
TSOP I
Top View
(not to scale)
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
Cypress Semiconductor Corporation
Document #: 38-15001 Rev. *E
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised November 15, 2004
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