鉂?/div>
On-Chip Precision Voltage Reference
Port 3
Port 2
Port 1
Port 0
PSoC鈩?Functional Overview
The PSoC鈩?family consists of many
Mixed-Signal Array with
On-Chip Controller
devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable component. A
PSoC device includes configurable blocks of analog and digital
logic, as well as programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application. Addi-
tionally, a fast CPU, Flash program memory, SRAM data mem-
ory, and configurable IO are included in a range of convenient
pinouts.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow all the device resources to be combined into a
complete custom system. Each CY8C21x34 PSoC device
includes four digital blocks and four analog blocks. Depending
on the PSoC package, up to 28 general purpose IO (GPIO) are
also included. The GPIO provide access to the global digital
and analog interconnects.
PSoC
CORE
SystemBus
Global Digital
Interconnect
SRAM
512 Bytes
Interrupt
Controller
SROM
Global Analog Interconnect
Flash 8K
Sleep and
Watchdog
CPU Core
(M8C)
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
Digital
PSoC
Block
Array
ANALOG SYSTEM
Analog
PSoC
Block
Array
Analog
Ref.
The PSoC Core
Digital
Clocks
POR and LVD
I2C
System Resets
Sw itch
Mode
Pump
Internal
Voltage
Ref.
Analog
Mux
SYSTEM RESOURCES
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO (inter-
nal main oscillator) and ILO (internal low speed oscillator). The
April 20, 2005
漏 Cypress Semiconductor Corp. 2004-2005 鈥?Document No. 38-12025 Rev. *G
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