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CY8C201A0-SX2I Datasheet

  • CY8C201A0-SX2I

  • CapSense Express⑩ -10 Configurable IOs with Slider

  • 12頁(yè)

  • CYPRESS

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CY8C201A0
CapSense Express鈩?/div>
-10 Configurable IOs
with Slider
Features
鈻?/div>
Overview
The CapSense Express
TM
controller allows the control of 10
IOs configurable as capacitive sensing buttons or as GPIOs
for driving LEDs or interrupt signals based on various button
conditions. The GPIOs are also configurable for waking up the
device from sleep based on an interrupt input.
The user has the ability to configure buttons, outputs, and
parameters, through specific commands sent to the I
2
C port.
The IOs have the flexibility in mapping to capacitive buttons
and as standard GPIO functions such as interrupt output or
input, LED drive and digital mapping of input to output using
simple logical operations. This enables easy PCB trace
routing and reduces the PCB size and stack up. CapSense
Express products are designed for easy integration into
complex products.
10 configurable IOs supporting
鉂?/div>
CapSense slider
鉂?/div>
LED drive
鉂?/div>
Interrupt outputs
鉂?/div>
WAKE on interrupt input
鉂?/div>
User defined input or output
2.4V to 5.25V operating voltage
Industrial temperature range: 鈥?0擄C to +85擄C
I
2
C slave interface for configuration
鉂?/div>
Selectable to 50 kHz,100 kHz and 400 kHz.
Reduce BOM cost
鉂?/div>
Internal oscillator - no external oscillators or crystal
鉂?/div>
Free development tool - no external tuning components
Low operating current
鉂?/div>
Active current: continuous sensor scan: 1.5 mA
鉂?/div>
Sleep current: no scan, continuous sleep: 2.6 uA
Available in 16-pin COL and 16-pin SOIC packages
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Architecture
The logic block diagram shows the internal architecture of
CY8C201A0.
The user can configure registers with parameters needed to
adjust the operation and sensitivity of the CapSense system.
CY8C201A0 supports a standard I
2
C serial communication
interface that allows the host to configure the device and to
read sensor information in real time through easy register
access.
鈻?/div>
鈻?/div>
The CapSense Express Core
The CapSense Express Core has a powerful configuration and
control block. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers. System
resources provide additional capability, such as a configurable
I
2
C slave communication interface and various system resets.
The Analog System is composed of the CapSense PSoC
block which supports capacitive sensing of up to 10 inputs.
Cypress Semiconductor Corporation
Document Number: 001-17349 Rev. *B
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised March 11, 2008
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CY8C201A0-SX2I 產(chǎn)品屬性

  • CY8C201A0

  • CapSense Express

  • 48

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 觸摸屏控制器

  • CapSense Express™ CY8C20xxx

  • 電容性

  • -

  • 10 個(gè)滑塊，5 個(gè)滑塊/5 個(gè)可配置

  • -

  • 可供

  • I²C

  • -

  • -

  • 2.4 V ~ 5.25 V

  • 1.5mA

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-SOIC（0.154"，3.90mm 寬）

  • 16-SOIC

  • 管件

  • 428-2044-ND - KIT CAPSENSE EXPRESS CY8C201A0

  • 428-2056-5

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