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CY8C20110-SX2I Datasheet

  • CY8C20110-SX2I

  • CapSenseLITE - 10 Configurable IOs

  • 314.99KB

  • 12頁(yè)

  • CYPRESS

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CY8C20110
CapSenseLITE
-
10 Configurable IOs
Features
鈻?/div>
Overview
The CapSenseLITE controller allows the control of ten IOs
configurable as capacitive sensing buttons or as GPIOs for
driving LEDs or interrupt signals based on various button
conditions. The GPIOs are also configurable for waking up the
device from sleep based on an interrupt input.
The user has the ability to configure buttons, outputs, and
parameters, through specific commands sent to the I
2
C port. The
IOs have the flexibility in mapping to capacitive buttons and as
standard GPIO functions such as interrupt output or input, LED
drive and digital mapping of input to output using simple logical
operations. This enables easy PCB trace routing and reduces
the PCB size and stack up. CapSenseLITE products are
designed for easy integration into complex products.
Ten configurable IOs supporting
鉂?/div>
CapSense buttons
鉂?/div>
LED drive
鉂?/div>
Interrupt outputs
鉂?/div>
WAKE on interrupt input
鉂?/div>
User defined input/output
2.4V to 5.25V operating voltage
Industrial temperature range: 鈥?0擄C to +85擄C
I
2
C slave interface for configuration
Reduce BOM cost
鉂?/div>
Internal oscillator - no external oscillators or crystal
鉂?/div>
Free development tool - no external tuning components
Low operating current
鉂?/div>
Active current: continuous sensor scan - 1mA
鉂?/div>
Sleep current: no scan, continuous sleep - 2.6uA
Available in 16-pin QFN and 16-pin SOIC packages
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Architecture
The logic block diagram illustrates the internal architecture of
CY8C20110.
The user is able to configure registers with parameters needed
to adjust the operation and sensitivity of the CapSense system.
CY8C20110 supports a standard I虜C serial communication
interface that allows the host to configure the device and to read
sensor information in real time through easy register access.
鈻?/div>
鈻?/div>
The CapSenseLITE Core
The CapSenseLITE Core has a powerful configuration and
control block. It encompasses SRAM for data storage, an
interrupt controller, along with sleep and watchdog timers.
System resources provide additional capability, such as a config-
urable I
2
C slave communication interface and various system
resets. The Analog system contains the CapSense PSoC block
and an internal 1.8V analog reference, which together support
capacitive sensing of up to 10 inputs.
Cypress Semiconductor Corporation
Document Number: 001-17345 Rev. *B
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?408-943-2600
Revised November 22, 2007
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CY8C20110-SX2I 產(chǎn)品屬性

  • CY8C201xx

  • CapSense Express

  • 48

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 觸摸屏控制器

  • CapSense Express™ CY8C20xxx

  • 電容性

  • -

  • 10 鍵

  • -

  • 可供

  • I²C

  • -

  • -

  • 2.4 V ~ 5.25 V

  • 1.5mA

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-SOIC（0.154"，3.90mm 寬）

  • 16-SOIC

  • 管件

  • 428-2043-ND - KIT CAPSENSE EXPRESS CY8C20110

  • 428-2047-5

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