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CY7C960-NC Datasheet

  • CY7C960-NC

  • Low Cost VMEbus Interface Controller Family

  • 10頁

  • CYPRESS

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CY7C960
CY7C961
Low Cost VMEbus Interface
Controller Family
Features
鈥?80-Mbyte-per-second block transfer rates
鈥?All VME64 transactions provided, including A64/D64,
A40/MD32 transfers
鈥?Auto Slot ID
鈥?CR/CSR space
鈥?All standard (Rev C) VMEbus transactions implemented
鈥?VMEbus Interrupter
鈥?No local CPU required
鈥?Programmable from VMEbus, serial PROM, or local bus
鈥?DRAM controller, including refresh
鈥?On-chip DMA controller
鈥?Local I/O controller
鈥?Flexible VMEbus address scheme
鈥?User-configured VMEbus response
鈥?64-pin TQFP, 10x10mm (CY7C960)
鈥?100-pin TQFP, 14x14mm (CY7C961)
Functional Description
The CY7C960 Slave VMEbus Interface Controller provides the
board designer with an integrated, full-featured VME64 inter-
face. This 64-pin device can be programmed to handle every
transaction defined in the VME64 specification. The CY7C961
is based upon the CY7C960: additional features include Re-
mote Master capability whereby the CY7C961 can be com-
manded to move data as a VMEbus master. The CY7C961 is
packaged in a 100-pin outline.
The CY7C960 contains all the circuitry needed to control large
DRAM arrays and local I/O circuitry without the intervention of
a local CPU. There are no registers to read or write, no com-
plex command blocks to be constructed in memory. The
CY7C960 simply fetches its own configuration parameters
during the power-on reset period. After reset the CY7C960
responds appropriately to VMEbus activity and controls local
circuitry transparently.
CY7C960 Logic Block Diagram
D64
STROBE
DENO*
DENIN*
DENIN1*
LADI
LAEN
LEDI
LEDO
ABEN*
LDS
REGION [3:0]
AM [5:0]
REGION/
AM TABLE
POWER-ON
RESET
GENERATOR
CY7C964 CONTROLLER
LOCAL ADDRESS
CONTROLLER
LA [7:1]
L WORD
SYSRESET*
CLK
AS*
DS0*
DS1*
DTACK*
WRITE*
IRQ*
IACK*
IACKIN*
IACKOUT*
TIMING
GENERATOR
CHIP SELECT
OUTPUT PATTERN
TABLE
CS[5:0]
VME CONTROL
INTERF
ACE
REFRESH
CONTROLLER
VME INTERRUPT
INTERF
ACE
DRAM
CONTROLLER
DATABYTE
LANE
DECODER
DATA BYTE
ENABLE
CONTROLLER
DBE [3:0]
LACK*
LOCAL
CONTROL
CIRCUIT
LDEN*
PREN*
SWDEN*
R/W
LIRQ*
RAS*
CAS*
ROW
COL
c960鈥?
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?CA 95134 鈥?/div>
408-943-2600
December 1994 鈥?Revised December 4, 1997

CY7C960-NC相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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