鈥?/div>
鈥?SMPTE-244M compliant for 4
fsc
composite video
Fully compatible with DVB-ASI
Operates from a single +5V or 鈥?V supply
44-pin PLCC package
Encodes both 8- and 10-bit parallel digital streams for
any rate from 16鈥?0 M characters/sec (160鈥?00
Mbits/sec serial)
Operates with CY7B9234 SMPTE HOTLink鈩?serializ-
er/transmitter
X
9
+ X
4
+ 1 scrambler and NRZI encoder may be by-
passed for raw data output
a CY7B9234 HOTLink transmitter, which then converts the
bit-parallel characters into a SMPTE-259M compatible
high-speed serial data stream.
This device performs both TRS (sync) detection and filtering,
data scrambling with the SMPTE-259M X
9
+ X
4
+ 1 algorithm,
and NRZ-to-NRZI encoding. These functions operate at any
character rate from 16- to 40 MHz. For those systems operat-
ing with non-SMPTE-259M compliant video streams (or for di-
agnostic purposes), the scrambler and NRZI encoding func-
tions can be disabled.
DVB-ASI Operation
The CY7C9235 also contains the necessary multiplexers, con-
trol inputs, and outputs, to sequence out a DVB-ASI compliant
video stream. DVB-ASI operation is enabled through activation
of a single input signal. This allows a single serial output port
to support both SMPTE and DVB data streams under software
or hardware control.
In DVB-ASI mode the CY7C9235 operates with two enable
signals (ENA and ENN) to allow data to be presented from
either synchronous (clocked) or asynchronous FIFOs. When
data is not available, the CY7C9235 ensures that the proper
fill character (K28.5) is generated by the attached CY7B9234
serializer.
The CY7C9235 operates from a single +5V or
鈭?V
supply. It is
available in a 44-pin PLCC space saving package.
Functional Description
SMPTE-259M Operation
The CY7C9235 is a CMOS integrated circuit designed to en-
code SMPTE-125M and SMPTE-244M bit-parallel digital char-
acters (or other data formats) using the SMPTE-259M encod-
ing rules. Following encoding, the characters are output as
bit-parallel characters ready for serialization. The encoded
outputs of the CY7C9235 are designed to be directly mated to
Logic Block Diagram
PD
9
(SVS)
TRS_DET
TRS FILTER / DETECTOR
PD
8
PD
7
PD
6
PD
5
PD
4
PD
3
PD
2
PD
1
PD
0
(SC/D)
TRS_FILT
SC/D_EN
SVS_EN
BYPASS
DVB_EN
ENA
ENN
Q
9
(SVS)
SMPTE SCRAMBLER
Q
8
10
NRZI ENCODER
10
10
Q
7
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
(SC/D)
10
INPUT REGISTER
10
MODE MULTIPLEXOR
OUTPUT REGISTER
ENA_OUT
CKW
OE
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
March 19, 1999
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