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CY7C68000-56PVCT Datasheet

  • CY7C68000-56PVCT

  • TX2 USB 2.0 UTMI Transceiver

  • 14頁(yè)

  • CYPRESS

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PRELIMINARY
CY7C68000
TX2鈩?USB 2.0 UTMI Transceiver
1.0
EZ-USB TX2錚?Features
The Cypress EZ-USB TX2錚?is a Universal Serial Bus (USB)
specification revision 2.0 transceiver, serial/deserializer, to a
parallel interface of either 16 bits at 30 MHz or eight bits at 60
MHz. The TX2 provides a high-speed physical layer interface
that operates at the maximum allowable USB 2.0 bandwidth.
This allows the system designer to keep the complex high-
speed analog USB components external to the digital ASIC
which decreases development time and associated risk. A
standard interface is provided that is USB 2.0-certified and is
compliant with Transceiver Macrocell Interface (UTMI) speci-
fication version 1.05 dated 3/29/01.
Two packages are defined for the family: 56-pin SSOP and 56-
pin QFN.
The function block diagram is shown in
Figure 1-1.
鈥?UTMI-compliant/USB-2.0-certified for device operation
鈥?Operates in both USB 2.0 high speed (HS), 480
Mbits/second, and full speed (FS), 12 Mbits/second
鈥?Serial-to-parallel and parallel-to-serial conversions
鈥?8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirec-
tional external data interface
鈥?Synchronous field and EOP detection on receive pack-
ets
鈥?Synchronous field and EOP generation on transmit
packets
鈥?Data and clock recovery from the USB serial stream
鈥?Bit stuffing/unstuffing; bit stuff error detection
鈥?Staging register to manage data rate variation due to
bit stuffing/unstuffing
鈥?16-bit 30-MHz, and 8-bit 60-MHz parallel interface
鈥?Ability to switch between FS and HS terminations and
signaling
鈥?Supports detection of USB reset, suspend, and resume
鈥?Supports HS identification and detection as defined by
the USB 2.0 Specification
鈥?Supports transmission of resume signaling
鈥?3.3V operation
鈥?Two package options鈥?6-pin QFN, and 56-pin SSOP
鈥?All required terminations, including 1.5K-ohm pull-up
on DPLUS, are internal to chip
鈥?Supports USB 2.0 test modes.
CY7C68000
CY7C68000
XTALIN/
OUT
OSC
20X
PLL
PLL_480
UTMI CLK
UTMI CLK
Full-Speed Rx
High-Speed Rx
USB
USB
2.0
XCVR
Traffic
Sync
Elasticity
Buffer
Fast
Digital
Rx
Fast
Digital
Tx
Digital
Rx
UTMI Rx Ctl
UTMI Rx Data 8/16
High-Speed Tx
BIDI Option
Also
Full-Speed Tx
Digital
Tx
UTMI Rx Data 8/16
UTMI Tx Ctl
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation
Document #: 38-08016 Rev. *E
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised November 2, 2004

CY7C68000-56PVCT相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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