3686AV
CY7C43646AV
CY7C43666AV
CY7C43686AV
3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO
Features
鈥?3.3V high-speed, low-power, First-In First-Out (FIFO)
memories with three independent ports (one bidirec-
tional 脳36, and two unidirectional 脳18)
鈥?1K 脳36/脳18脳2 (CY7C43646AV)
鈥?4K 脳36/脳18脳2 (CY7C43666AV)
鈥?16K 脳36/脳18脳2 (CY7C43686AV)
鈥?0.25-micron CMOS for optimum speed/power
鈥?High-speed 133-MHz operation (7.5-ns Read/Write
cycle times)
鈥?Low power
鈥?I
CC
= 60 mA
鈥?I
SB
= 10 mA
鈥?Fully asynchronous and simultaneous Read and Write
operation permitted
鈥?Mailbox bypass register for each FIFO
鈥?Parallel and serial programmable Almost Full and
Almost Empty flags
鈥?Retransmit function
鈥?Standard or FWFT user-selectable mode
鈥?Partial and master reset
鈥?Big or Little Endian format for word or byte bus sizes
鈥?128-pin TQFP packaging
鈥?Easily expandable in width and depth
Logic Block Diagram
MBF1
CLKA
CSA
W/RA
ENA
MBA
RT2
1K/4K/16K
脳 36
Dual Ported
Memory
(FIFO1)
Output
Bus Matching
Input
Register
Register
Port A
Control
Logic
Mail1
Register
B
0鈥?7
CLKB
Output
Port B
Control
Logic
RENB
CSB
SIZEB
MBB
RTI
MRS1
PRS1
FIFO1,
Mail1
Reset
Logic
Write
Pointer
Read
Pointer
FFA/IRA
AFA
Status
Flag Logic
Common
Port Logic
(B and C)
EFB/ORB
AEB
SPM
FS0/SD
FS1/SEN
A
0鈥?5
EFA/ORA
AEA
Programmable
Flag Offset
Registers
Timing
Mode
BE/FWFT
FFC/IRC
AFC
Status
Flag Logic
Read
Pointer
1
Pointer
Input
Bus Matching
FIFO2,
Mail2
Reset
Logic
Input
Register
MRS2
PRS2
1K/4K/16K
脳 36
Dual Ported
Memory
(FIFO2)
Mail2
Register
Output
Register
C
0鈥?7
CLKC
Port C
Control
Logic
WENC
SIZEC
MBC
MBF2
Cypress Semiconductor Corporation
Document #: 38-06026 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 26, 2002
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