鈥?/div>
鈥?I
SB
= 10 mA
Fully asynchronous and simultaneous read and write
operation permitted
Mailbox bypass register for each FIFO
Parallel Programmable Almost Full and Almost Empty
flags
Retransmit function
Standard or FWFT mode user selectable
120-pin TQFP packaging
Easily expandable in width and depth
Logic Block Diagram
MBF1
CLKA
CSA
W/RA
ENA
MBA
RT2
Port A
Control
Logic
Input
Register
Mail1
Register
CLKB
CSB
W/RB
ENB
MBB
RT1
Register
RST1
FIFO1,
Mail1
Reset
Logic
Write
Pointer
Read
Pointer
FFA/IRA
AFA
Status
Flag Logic
Output
1K/4K/16K
x36
Dual Ported
Memory
Port B
Control
Logic
EFB/ORB
AEB
FS0
FS1
A
0鈥?5
EFA/ORA
AEA
Programmable
Flag Offset
Registers
Timing
Mode
B
0鈥?5
FWFT/STAN
Status
Flag Logic
Write
Pointer
Read
Pointer
FFB/IRB
AFB
Output
Register
256/512/1K
4K/16K x36
Dual Ported
Memory
Mail2
Register
MBF2
Cypress Semiconductor Corporation
Document #: 38-06019 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
Input
Register
FIFO2,
Mail2
Reset
Logic
RST2
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 26, 2002
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