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CY7C408A-35VC Datasheet

  • CY7C408A-35VC

  • 64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO

  • 347.65KB

  • 16頁

  • CYPRESS

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1CY 7C40 9A
CY7C408A
CY7C409A
64 x 8 Cascadable FIFO
64 x 9 Cascadable FIFO
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
64 x 8 and 64 x 9 first-in first-out (FIFO) buffer memory
35-MHz shift in and shift out rates
Almost Full/Almost Empty and Half Full flags
Dual-port RAM architecture
Fast (50-ns) bubble-through
Independent asynchronous inputs and outputs
Output enable (CY7C408A)
Expandable in word width and FIFO depth
5V
鹵
10% supply
TTL complete
Capable of withstanding greater than 2001V electro-
static discharge voltage
鈥?300-mil, 28-pin DIP
same order as it was stored on the DO
0
鈥?DO
8
output pins
under the control of the shift out (SO) input when the output
ready (OR) control signal is HIGH. If the FIFO is full (IR LOW),
pulses at the SI input are ignored; if the FIFO is empty (OR
LOW), pulses at the SO input are ignored.
The IR and OR signals are also used to connect the FIFOs in
parallel to make a wider word or in series to make a deeper
buffer, or both.
Parallel expansion for wider words is implemented by logically
ANDing the IR an OR outputs (respectively) of the individual
FIFOs together (Figure
5).
The AND operation insures that all
of the FIFOs are either ready to accept more data (IR HIGH)
or ready to output data (OR HIGH) and thus compensate for
variations in propagation delay times between devices.
Serial expansion (cascading) for deeper buffer memories is
accomplished by connecting data outputs of the FIFO closet
to the data source (upstream device) to the data inputs of the
following (downstream) FIFO (Figure
4).
In addition, to insure
proper operation, the SO signal of the upstream FIFO must be
connected to the OR output of the upstream FIFO. In this serial
expansion configuration, the IR and OR signals are used to
pass data through the FIFOs.
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital
machines of widely differing operating frequencies. The high
shift in and shift out rates of these FIFOs, and their throughput
rate due to the fast bubblethrough time, which is due to their
dual-port RAM architecture, make them ideal for high-speed
communications and controllers.
Functional Description
The CY7C408A and CY7C409A are 64-word deep by 8- or
9-bit wide first-in first-out (FIFO) buffer memories. In addition
to the industry-standard handshaking signals, almost full/al-
most empty (AFE) and half-full (HF) flags are provided.
AFE is HIGH when the FIFO is almost full or almost empty,
otherwise AFE is LOW. HF is HIGH when the FIFO is half full,
otherwise HF is LOW.
The CY7C408A has an output enable (OE) function.
The memory accepts 8- or 9-bit parallel words as its inputs (DI
0
鈥?DI
8
) under the control of the shift in (SI) input when the input
ready (IR) control signal is HIGH. The data is output, in the
Logic Block Diagram
SI
IR
INPUT
CONTROL
LOGIC
WRITE POINTER
WRITEMULTIPLEXER
ALMOST FULL/
ALMOST EMPTY
HALF FULL
AFE
HF
DO 0
.
.
.
DO 7
DATAOUT
Pin Configurations
AFE
HF
IR
SI
DI 0
DI 1
GND
1
28
2
27
3
26
4
25
5
24
6
23
7C408A
7 7C409A 22
21
8
9
20
10
19
11
18
12
17
13
16
15
14
VCC
MR
SO
OR
DO0
DO1
GND
DO2
DO3
DO4
DO5
DO6
DO7
OE (7C408A)
DO8 (7C409A)
C408A鈥?
C408A鈥?
DI 0
.
.
.
DI 7
(7C409A)DI 8
DATA IN
MEMORY
ARRAY
READ MULTIPLEXER
MR
MASTER
RESET
READ POINTER
OUTPUT
CONTROL
LOGIC
DI 2
DI 3
DO 8 (7C409A)
DI 4
DI 5
DI 6
OE (7C408A)
DI 7
OR
(7C408A) NC
(7C409A) DI8
SO
Flag Definitions
HF
L
L
H
H
AFE
H
L
L
H
Words Stored
0-8
9 - 31
32 - 55
56 - 64
DI 0
DI 1
GND
DI 2
DI 3
DI 4
DI 5
4 3 2 1 28 27 26
25
5
24
6
23
7
7C408A
22
8
7C409A
21
9
20
10
19
11
12 13 14 15 1617 18
OR
DO 0
DO 1
GND
DO 2
DO 3
DO 4
C408A鈥?
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
July 1986 鈥?Revised July 1994

CY7C408A-35VC相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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