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CY7C375I-83UMB Datasheet

  • CY7C375I-83UMB

  • UltraLogic 128-Macrocell Flash CPLD

  • 17頁

  • CYPRESS

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USE ULTRA37000鈩?/div>
FOR ALL NEW DESIGNS
CY7C375i
UltraLogic鈩?128-Macrocell Flash CPLD
Features
鈥?128 macrocells in eight logic blocks
鈥?128 I/O pins
鈥?Five dedicated inputs including 4 clock pins
鈥?In-System Reprogrammable (ISR鈩? Flash technology
鈥?JTAG Interface
鈥?Bus Hold capabilities on all I/Os and dedicated inputs
鈥?No hidden delays
鈥?High speed
鈥?f
MAX
= 125 MHz
鈥?t
PD
= 10 ns
鈥?t
S
= 5.5 ns
鈥?t
CO
= 6.5 ns
鈥?Fully PCI compliant
鈥?3.3V or 5.0V I/O operation
鈥?Available in 160-pin TQFP, CQFP, and PGA packages
Functional Description
The CY7C375i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i鈩?family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C375i is
designed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
Like all of the UltraLogic鈩?F
LASH
370i devices, the CY7C375i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally,
because of the superior routability of the F
LASH
370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
Inputs
1
INPUT
MACROCELL
4
Clock
Inputs
4
INPUT/CLOCK
MACROCELLS
4
36
PIM
16
36
16
36
16
36
16
LOGIC
BLOCK
16 I/Os
I/O
112
鈥揑/O
127
Logic Block Diagram
I/O
0
鈥揑/O
15
16 I/Os
LOGIC
BLOCK
A
16 I/Os
LOGIC
BLOCK
36
16
36
16
36
16
36
16
H
LOGIC
BLOCK
16 I/Os
I/O
16
鈥揑/O
31
B
16 I/Os
LOGIC
BLOCK
G
LOGIC
BLOCK
16 I/Os
I/O
96
鈥揑/O
111
I/O
32
鈥揑/O
47
C
16 I/Os
LOGIC
BLOCK
F
LOGIC
BLOCK
16 I/Os
I/O
80
鈥揑/O
95
I/O
48
鈥揑/O
63
D
64
E
64
I/O
64
鈥揑/O
79
Selection Guide
7C375i鈥?25 7C375i鈥?00 7C375i鈥?3
Maximum Propagation Delay
[1]
Minimum Set-Up, t
S
Maximum Clock to Output
[1]
, t
CO
Typical Supply Current, I
CC
, t
PD
10
5.5
6.5
125
12
6
7
125
15
8
8
125
7C375iL鈥?3
15
8
8
75
7C375i鈥?6 7C375iL鈥?6 Unit
20
10
10
125
20
10
10
75
ns
ns
ns
mA
Note:
1. The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V
Cypress Semiconductor Corporation
Document #: 38-03029 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised May 10, 2004

CY7C375I-83UMB相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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