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CY7C346-30RMB Datasheet

  • CY7C346-30RMB

  • USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD...

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USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
CY7C346
128-Macrocell MAX
廬
EPLD
Features
鈥?128 macrocells in eight logic array blocks (LABs)
鈥?20 dedicated inputs, up to 64 bidirectional I/O pins
鈥?Programmable interconnect array
鈥?0.8-micron double-metal CMOS EPROM technology
鈥?Available in 84-pin CLCC, PLCC, and 100-pin PGA,
PQFP
The 128 macrocells in the CY7C346 are divided into eight
LABs, 16 per LAB. There are 256 expander product terms, 32
per LAB, to be used and shared by the macrocells within each
LAB.
Each LAB is interconnected through the programmable inter-
connect array, allowing all signals to be routed throughout the
chip.
The speed and density of the CY7C346 allow it to be used in
a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 25 times the functionality
of 20-pin PLDs, the CY7C346 allows the replacement of over
50 TTL devices. By replacing large amounts of logic, the
CY7C346 reduces board space, part count, and increases
system reliability.
Functional Description
The CY7C346 is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX
廬
architecture is
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
Logic Block Diagram
.. 1
. 78
. 79
80
. 83
. 84
.. 2
.. 5
.. 6
.. 7
(C7) [16]
(A10) [9]
(B9) [10]
(A9) [11]
(A8) [14]
(B7) [15]
(A7) [17]
(C6) [20]
(A5) [21]
(B5) [22]
. INPUT/CLK
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
.....
INPUT
SYSTEM CLOCK
LAB A
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
LAB H
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL 121鈥?28
LAB G
MACROCELL 104
MACROCELL 103
MACROCELL 102
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
P
I
A
MACROCELL 105鈥?12
LAB F
MACROCELL 88
MACROCELL 87
MACROCELL 86
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 86鈥?6
LAB E
49
50
51
52
53
54
55
56
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
72
71
70
69
68
67
66
65
[58]
[57]
[56]
[55]
[54]
[53]
[52]
[51]
(M4) NC
(N3) NC
(M3) 55
(N2) 54
(M2) 53
(N1) 52
(L2) 51
(M1) 50
INPUT [59]
INPUT [60]
INPUT [61]
INPUT [64]
INPUT [65]
INPUT [66]
INPUT [67]
INPUT [70]
INPUT [71]
INPUT [72]
(N4)
(M5)
(N5)
(N6)
(M7)
(L7)
(N7)
(L8)
(N9)
(M9)
.
.
.
.
.
.
.
.
.
.
36
37
38
41
42
43
44
47
48
49
8 (B13) [1]
9 (C12) [2]
10 (A13) [3]
11 (B12) [4]
12 (A12) [5]
13 (11) [6]
NC (A11) [7]
NC (B10) [8]
1
2
3
4
5
6
7
8
[100] (C13) NC
[99] (D12) NC
[98] (D13) 77
[97] (E12) 76
[96] (E13) 75
[95] (F11) 74
[92] (G13) 73
[91] (G11) 72
MACROCELL 9鈥?6
LAB B
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
14 (A4)
15 (B4)
16 (A3)
17 (A2)
18 (B3)
21 (A1)
NC (B2)
NC (B1)
[23]
[24]
[25]
[26]
[27]
[28]
[29]
[30]
17
18
19
20
21
22
23
24
[90]
[89]
[86]
[85]
[84]
[83]
[82]
[81]
(G12) NC
(H13) NC
(J13) 71
(J12) 70
(K13) 69
(K12) 68
(L13) 67
(L12) 64
MACROCELL 25鈥?2
LAB C
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
22 (C2) [31]
25 (C1) [32]
26 (D2) [33]
27 (D1) [34]
28 (E2) [35]
29 (E1) [36]
NC (F1) [39]
NC (G2) [40]
33
34
35
36
37
38
39
40
[80]
[79]
[78]
[77]
[76]
[75]
[74]
[73]
(M13)
(M12)
(N13)
(M11)
(N12)
(N11)
(M10)
(N10)
NC
NC
63
60
59
58
57
56
MACROCELL 41鈥?8
LAB D
30 (G3) [41]
31 (G1) [42]
32 (H3) [45]
33 (J1) [46]
34 (J2) [47]
35 (K1) [48]
NC (K2) [49]
NC (L1) [50]
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL 57鈥?64
3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8)
16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6)
[18, 19, 43, 44, 68, 69, 93, 94]
[12, 13, 37, 38, 62, 63, 87, 88]
VCC
GND
MACROCELL 73鈥?80
() 鈥?PERTAIN TO 100-PIN PGA PACKAGE
[ ] 鈥揚(yáng)ERTAIN TO 100-PIN PQFP PACKAGE
Cypress Semiconductor Corporation
Document #: 38-03005 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised April 19, 2004

CY7C346-30RMB相關(guān)型號(hào)PDF文件下載

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    64K/128K x 8/9 Dual-Port Static RAM
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    64K/128K x 8/9 Dual-Port Static RAM
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    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
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    64K/128K x 8/9 Dual-Port Static RAM
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    64K/128K x 8/9 Dual-Port Static RAM
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    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
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    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
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    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
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    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
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