77
CY7C277
32K x 8 Reprogrammable Registered PROM
Features
鈥?Windowed for reprogrammability
鈥?CMOS for optimum speed/power
鈥?High speed
鈥?30-ns address set-up
鈥?15-ns clock to output
鈥?Low power
鈥?60 mW (commercial)
鈥?715 mW (military)
鈥?Programmable address latch enable input
鈥?Programmable synchronous or asynchronous output
enable
鈥?On-chip edge-triggered output registers
鈥?EPROM technology, 100% programmable
鈥?Slim 300-mil, 28-pin plastic or hermetic DIP
鈥?/div>
5V
鹵10%
V
CC
, commercial and military
鈥?TTL-compatible I/O
鈥?Direct replacement for bipolar PROMs
鈥?Capable of withstanding greater than 2001V static dis-
charge
Logic Block Diagram
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
X
ADDRESS
ROW
DECODER
1 OF 256
256 x 1024
PROGRAMMABLE
ARRAY
8-BIT
1 OF 128
MUX
Pin Configurations
O
7
O
6
O
5
8-BIT
EDGE-
TRIGGERED
REGISTER
DIP/Flatpack
Top View
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A
10
A
11
A
12
A
13
A
14
ALE
CP
E/E
S
O
7
O
6
O
5
O
4
O
3
15-BIT
ADDRESS
TRANSPARENT/
LATCH
O
4
O
3
O
2
O
1
Y
ADDRESS
COLUMN
DECODER
1 OF 32
ALE
PROGRAMMABLE
CP/ALE OPTIONS
O
0
CP
ALE
LCC/PLCC (Opaque Only)
Top View
E/E
S
CP
D
C
Q
PROGRAMMABLE
MULTIPLEXER
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
O
0
4 3 2 1 32 31 30
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
14151617 181920
O1
O2
GND
NC
O3
O4
O5
A7
A8
A9
NC
V
CC
A10
A11
A
12
A
13
A
14
NC
ALE
CP
E/E
S
O
7
O
6
Selection Guide
7C277-30
Minimum Address Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum Operating
Current (mA)
Com鈥檒
Mil
30
15
120
7C277-40
40
20
120
130
7C277-50
50
25
120
130
Cypress Semiconductor Corporation
Document #: 38-04006 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised March 4, 2002
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