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CY7C271A-35WC Datasheet

  • CY7C271A-35WC

  • 32K x 8 Power Switched and Reprogrammable PROM

  • 169.81KB

  • 10頁

  • CYPRESS

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1CY7C271A
CY7C271A
32K x 8 Power Switched and
Reprogrammable PROM
Features
鈥?CMOS for optimum speed/power
鈥?Windowed for reprogrammability
鈥?High speed
鈥?25 ns (Commercial)
鈥?Low power
鈥?275 mW (Commercial)
鈥?Super low standby power
鈥?Less than 85 mW when deselected
鈥?EPROM technology 100%programmable
鈥?Slim 300-mil package
鈥?Direct replacement for bipolar PROMs
鈥?Capable of withstanding >4001V static discharge
automatically powers down into a low-power stand-by mode.
The CY7C271A is packaged in the 300-mil slim package and
is available in a cerDIP package equipped with an erasure
window to provide for reprogrammability. When exposed to UV
light, the PROM is erased and can be reprogrammed. The
memory cells utilize proven EPROM floating gate technology
and byte-wide intelligent programming algorithms.
The CY7C271A offers the advantages of lower power,
superior performance, and programming yield. The EPROM
cell requires only 12.5V for the super voltage, and low current
requirements allow for gang programming. The EPROM cells
allow each memory location to be tested 100% because each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each PROM is also tested for AC perfor-
mance to guarantee that after customer programming, the
product will meet DC and AC specification limits.
Reading the 7C271A is accomplished by placing active LOW
signals on CS
1
and CE, and an active HIGH on CS
2
. The
contents of the memory location addressed by the address
lines (A
0
鈥揂
14
) will become available on the output lines
(O
0
鈥揙
7
).
Functional Description
The CY7C271A is a high-performance 32,768-word by 8-bit
CMOS PROM. When disabled (CE HIGH), the 7C271A
Logic Block Diagram
O
7
Pin Configurations
DIP/Flatpack
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
O
3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A
10
A
11
A
12
A
13
A
14
CS
1
CS
2
CE
O
7
O
6
O
5
O
4
O
3
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Y
ADDRESS
X
ADDRESS
256 x 1024
PROGRAMABLE
ARRAY
8 x 1 OF 128
MULTIPLEXER
O
6
O
5
O
4
O
2
PLCC
Top View
A5
A6
A7
NC
VCC
A8
PS
A
4
A
3
A
2
A
1
A
0
NC
O
0
4 3 2 1 28 27 26
25
5
24
6
23
7
22
8
21
9
20
10
19
11
12 13 141516 17 18
O1
O2
GND
NC
O3
O4
O5
E
CLR
E
S
CP
NC
O
7
O
6
O
1
POWER-DOWN
O
0
CE
CS
1
CS
2
Cypress Semiconductor Corporation
Document #: 38-04013 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 28, 2002

CY7C271A-35WC相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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